參數(shù)資料
型號： 37C672
廠商： SMSC Corporation
英文描述： ENHANCED SUPER I/O CONTROLLER WITH FAST IR
中文描述： 增強(qiáng)的超級I / O控制器，快速紅外線
文件頁數(shù)： 55/173頁
文件大小： 965K
代理商： 37C672
3802 GROUP USER’S MANUAL
3-22
APPENDIX
3.3 Notes on use
(1) Sequence for switching an external interrupt
detection edge
Clear an interrupt enable bit to “0” (interrupt disabled)
Switch the detection edge
Clear an interrupt request bit to “0” (no interrupt requ-
est issued)
Set the interrupt enable bit to “1” ( interrupt enabled )
3.3 Notes on use
3.3.1 Notes on interrupts
When the external interrupt detection edge must be
switched, make sure the following sequence.
Reason
The interrupt circuit recognizes the switching of the
detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
(2) Bit 7 of the interrupt control register 2
Fix the bit 7 of the interrupt control register 2
(Address:003F16) to “0”.
Figure 3.3.1 shows the structure of the interrupt
control register 2.
Fig. 3.3.1 Structure of interrupt control register 2
3.3.2 Notes on the serial I/O1
(1) Stop of data transmission
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
the transmit enable bit to “0” (transmit disabled), and clear the serial I/O enable bit to “0” (serial I/O1 disabled)in
the following cases :
q when stopping data transmission during transmitting data in the clock synchronous serial I/O mode
q when stopping data transmission during transmitting data in the UART mode
q when stopping only data transmission during transmitting and receiving data in the UART mode
Reason
Since transmission is not stopped and the transmission circuit is not initialized even if the serial I/O1 enable bit
is cleared to “0” (serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK1,
______
and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer
register in this state, the data is transferred to the transmit shift register and start to be shifted. When the serial
I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and ti may cause
an operation failure to a microcomputer.
(2) Stop of data reception
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear
the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (serial I/O disabled) in the
following case :
q when stopping data reception during receiving data in the clock synchronous serial I/O mode
Clear the receive enable bit to “0” (receive disabled) in the following cases :
q when stopping data reception during receiving data in the UART mode
q when stopping only data reception during transmitting and receiving data in the UART mode
b7
b0
Interrupt control register 2
Address 003F16
Interrupt enable bits
Not used
Fix this bit to “0”
0
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