參數(shù)資料
型號: 37C672
廠商: SMSC Corporation
英文描述: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
中文描述: 增強的超級I / O控制器,快速紅外線
文件頁數(shù): 44/173頁
文件大小: 965K
代理商: 37C672
3802 GROUP USER'S MANUAL
3-12
APPENDIX
3.1 Electrical characteristics
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”.
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
Serial I/O2 input set up time
Serial I/O1 input hold time
Serial I/O2 input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
tsu(RXD–SCLK1)
tsu(SIN2–SCLK2)
th(SCLK1–RXD)
th(SCLK2–SIN2)
Symbol
Parameter
Limits
Min.
s
ns
Unit
2
125
50
200
80
800
1000
370
400
370
400
220
200
100
200
Typ.
Max.
Table 3.1.20 Switching characteristics (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85
°C, unless otherwise noted)
Table 3.1.19 Timing requirements (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85
°C, unless otherwise noted)
Serial I/O1 clock output “H” pulse width
Serial I/O2 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O2 output delay time (Note 2)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output valid time (Note 2)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
140
200
30
40
30
Symbol
Parameter
Limits
Min.
ns
Unit
tc(SCLK1)/2–30
tc(SCLK2)/2–160
tc(SCLK1)/2–30
tc(SCLK2)/2–160
–30
0
10
Typ.
Max.
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
td(SCLK1–TXD)
td(SCLK2–SOUT2)
tv(SCLK1–TXD)
tv(SCLK2–SOUT2)
tr(SCLK1)
tf(SCLK1)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Test conditions
Fig. 3.1.1
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”.
3: XOUT pin excluded.
3.1.12 Timing requirements and Switching characteristics (Extended operating temperature version)
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