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參數(shù)資料
| 型號(hào)： | 37C669 |
| 廠商： | SMSC Corporation |
| 英文描述： | DIODE SCHOTTKY SINGLE 25V 200mW 0.5V-vf 200mA-IFM 30mA-IF 2uA-IR SOD-323 3K/REEL |
| 中文描述： | 電腦98/99順從超級(jí)I / O軟盤(pán)控制器與紅外線支持 |
| 文件頁(yè)數(shù)： | 85/164頁(yè) |
| 文件大?。?/td> | 621K |
| 代理商： | 37C669 |
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27
DATA RATE SELECT REGISTER (DSR)
Address 3F4 WRITE ONLY
This register is write only. It is used to program
the data rate, amount of write precompensation,
power down status, and software reset.
The
data
rate
is
programmed
using
the
Configuration Control Register (CCR) not the
DSR, for PC/AT and PS/2 Model 30 and
Microchannel applications.
Other applications
can set the data rate in the DSR. The data rate
of the floppy controller is the most recent write
of either the DSR or CCR.
The DSR is
unaffected by a software reset.
A hardware
reset
will
set
the
DSR
to
02H,
which
corresponds to the default precompensation
setting and 250 kbps.
BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy
controller.
See Table 13 for the settings
corresponding to the individual data rates. The
data rate select bits are unaffected by a
software reset, and are set to 250 kbps after a
hardware reset.
BIT
2
through
4
PRECOMPENSATION
SELECT
These three bits select the value of write
precompensation that will be applied to the
WDATA output signal.
Table 12 shows the
precompensation values for the combination of
these bits settings.
Track 0 is the default
starting track number to start precompensation.
this starting track number can be changed by
the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy
controller into Manual Low Power mode. The
floppy controller clock and data separator
circuits will be turned off.
The controller will
come out of manual low power mode after a
software reset or access to the Data Register or
Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the
DOR RESET (DOR bit 2) except that this bit is
self clearing.
Table 10 - Precompensation Delays
7
6
5
4
3
2
1
0
S/W
RESET
POWER
DOWN
0
PRE-
COMP2
PRE-
COMP1
PRE-
COMP0
DRATE
SEL1
DRATE
SEL0
RESET
COND.
0
1
0
PRECOMP
432
PRECOMPENSATION DELAY
111
001
010
011
100
101
110
000
0.00 ns-DISABLED
41.67 ns
83.34 ns
125.00 ns
166.67 ns
208.33 ns
250.00 ns
Default (See Table 14)
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相關(guān)代理商/技術(shù)參數(shù) |
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| 37C672 | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:ENHANCED SUPER I/O CONTROLLER WITH FAST IR |
| 37C67X | 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:ENHANCED SUPER I/O CONTROLLER WITH FAST IR |
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