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參數(shù)資料
| 型號： | 37C669 |
| 廠商： | SMSC Corporation |
| 英文描述： | DIODE SCHOTTKY SINGLE 25V 200mW 0.5V-vf 200mA-IFM 30mA-IF 2uA-IR SOD-323 3K/REEL |
| 中文描述： | 電腦98/99順從超級I / O軟盤控制器與紅外線支持 |
| 文件頁數(shù)： | 158/164頁 |
| 文件大?。?/td> | 621K |
| 代理商： | 37C669 |
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93
8.
Peripheral asserts nWAIT, indicating to the
host that any hold time requirements have
been
satisfied
and
acknowledging
the
termination of the cycle.
9.
Chip may modify nWRITE and nPDATA in
preparation for the next cycle.
EPP 1.9 Read
The timing for a read operation (data) is shown
in timing diagram EPP Read Data cycle.
IOCHRDY is driven active low at the start of
each EPP read and is released when it has been
determined that the read cycle can complete.
The read cycle can complete under the following
circumstances:
1.
If the EPP bus is not ready (nWAIT
is
active low) when nDATASTB goes active
then the read can complete when nWAIT
goes inactive high.
2.
If the EPP bus is ready (nWAIT is inactive
high) then the chip must wait for it to go
active low before changing the state of
WRITE or before nDATASTB goes active.
The read can complete once nWAIT
is
determined inactive.
Read Sequence of Operation
1.
The host selects an EPP register and drives
nIOR active.
2.
The chip drives IOCHRDY inactive (low).
3.
If WAIT is not asserted, the chip must wait
until WAIT is asserted.
4.
The chip tri-states the PData bus and
deasserts nWRITE.
5.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR
is set and the nWRITE signal is valid.
6.
Peripheral drives PData bus valid.
7.
Peripheral deasserts nWAIT,
indicating
that PData is valid and the chip may
begin the termination phase of the cycle.
8.
a)
The chip latches the data from the
PData
bus
for
the
SData
bus,
deasserts nDATASTB or nADDRSTRB,
this
marks
the
beginning
of
the
termination phase.
b)
The chip drives the valid data onto the
SData
bus
and
asserts
(releases)
IOCHRDY
allowing
the
host
to
complete the read cycle.
9.
Peripheral tri-states the PData bus and
asserts nWAIT, indicating to the host that
the PData bus is tri-stated.
10. Chip
may modify nWRITE,
PDIR
and
nPDATA in preparation for the next cycle.
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the
configuration register, the standard and bi-
directional modes are also available. If no EPP
Read, Write or Address cycle is currently
executing, then the PDx bus is in the standard or
bi-directional mode, and all output signals
(STROBE, AUTOFD, INIT) are as set by the
SPP Control Port and direction is controlled by
PCD of the Control port.
In EPP mode, the system timing is closely
coupled to the EPP timing. For this reason, a
watchdog timer is required to prevent system
lockup. The timer indicates if more than 10usec
have elapsed from the start of the EPP cycle
(nIOR or nIOW asserted) to the end of the
cycle nIOR or nIOW deasserted). If a time-out
occurs, the current EPP cycle is aborted and the
time-out condition is indicated in Status bit 0.
Software Constraints
Before an EPP cycle is executed, the software
must ensure that the control register bits D0, D1
and D3 are set to zero. Also, bit D5 (PCD) is a
logic "0" for an EPP write or a logic "1" for and
EPP read.
EPP 1.7 Write
The timing for a write operation (address or
data) is shown in timing diagram EPP 1.7 Write
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