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參數(shù)資料
| 型號： | 30044-23 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low Power Integrated x86-Compatible with MMX Support 32-Bit Geode GXm Processor(低功耗集成兼容X86帶有MMX的32位 Geode GXm技術處理器) |
| 中文描述： | 32-BIT, 200 MHz, MICROPROCESSOR, CPGA320 |
| 封裝： | SPGA-320 |
| 文件頁數(shù)： | 147/244頁 |
| 文件大小： | 4496K |
| 代理商： | 30044-23 |
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Revision 3.1
147
www.national.com
Integrated Functions (
Continued
)
G
10:3
H_BLK_START
Horizontal Blank Start:
This field represents the character clock count at which the horizontal
blanking signal becomes active minus 1. The field [10:0] may be programmed with the pixel count
minus 1, although bits [2:0] are ignored. The blank start position is programmable on 8-pixel bound-
aries only.
Reserved:
These bits are readable and writable but have no effect.
Note:
A minimum of four character clocks is required for the horizontal blanking portion of a line in order for the timing generator to
function correctly.
2:0
RSVD
GX_BASE+8338h-833Bh
DC_H_TIMING_3 Register (R/W)
Default Value = xxxxxxxxh
31:27
26:19
RSVD
Reserved:
Set to 0.
Horizontal Sync End:
This field represents the character clock count at which the CRT horizontal
sync signal becomes inactive minus 1. The field [26:16] may be programmed with the pixel count
minus 1, although bits [18:16] are ignored. The sync end position is programmable on 8-pixel bound-
aries only.
Reserved:
These bits are readable and writable but have no effect.
Reserved:
Set to 0.
Horizontal Sync Start:
This field represents the character clock count at which the CRT horizontal
sync signal becomes active minus 1. The field [10:0] may be programmed with the pixel count minus
1, although bits [2:0] are ignored. The sync start position is programmable on 8-pixel boundaries
only.
Reserved:
These bits are readable and writable but have no effect.
Note:
This register should also be programmed appropriately for flat panel only display since the horizontal sync transition deter-
mines when to advance the vertical counter.
H_SYNC_END
18:16
15:11
10:3
RSVD
RSVD
H_SYNC_START
2:0
RSVD
GX_BASE+833Ch-833Fh
C_FP_H_TIMING Register (R/W)
Default Value = xxxxxxxxh
31:27
26:16
RSVD
Reserved:
Set to 0.
Flat Panel Horizontal Sync End:
This field represents the pixel count at which the flat panel hori-
zontal sync signal becomes inactive minus 1.
Reserved:
Set to 0.
Flat Panel Horizontal Sync Start:
This field represents the pixel count at which the flat panel hori-
zontal sync signal becomes active minus 1.
Note:
All values are specified in pixels rather than character clocks to allow precise control over sync position. Note, however, that for
flat panels which combine two pixels per panel clock, these values should be odd numbers (even pixel boundary) to guarantee
that the sync signal will meet proper setup and hold times.
FP_H_SYNC
_END
RSVD
FP_H_SYNC
_START
15:11
10:0
GX_BASE+8340h-8343h
DC_V_TIMING_1 Register (R/W)
Default Value = xxxxxxxxh
31:27
26:16
RSVD
V_TOTAL
Reserved:
Set to 0.
Vertical Total:
This field represents the total number of lines for a given frame scan minus 1. Note
that the value is necessarily greater than the V_ACTIVE field because it includes border lines and
blanked lines. If the display is interlaced, the total number of lines must be odd, so this value should
be an even number.
Reserved:
Set to 0.
Vertical Active:
This field represents the total number of lines for the displayed portion of a frame
scan minus 1. Note that for flat panels, if this value is less than the panel active vertical resolution
(V_PANEL), the parameters V_BLANK_START, V_BLANK_END, V_SYNC_START, and
V_SYNC_END should be reduced by the following value (V_ADJUST) to achieve vertical centering:
V_ADJUST = (V_PANEL - V_ACTIVE) / 2
If the display is interlaced, the number of active lines should be even, so this value should be an odd
number.
Note:
All values are specified in lines.
15:11
10:0
RSVD
V_ACTIVE
GX_BASE+8344h-8347h
DC_V_TIMING_2 Register (R/W)
Default Value = xxxxxxxxh
31:27
26:16
RSVD
Reserved:
Set to 0.
Vertical Blank End:
This field represents the line at which the vertical blanking signal becomes
inactive minus 1. If the display is interlaced, no border is supported, so this value should be identical
to V_TOTAL.
Reserved:
Set to 0.
V_BLANK_END
15:11
RSVD
Table 4-32. Display Controller Timing Registers (Continued)
Bit
Name
Description
相關PDF資料 |
PDF描述 |
|---|---|
| 30046-23 | Low Power Integrated x86-Compatible 32-Bit Geode GXLV Processor(低功耗集成兼容X86的32位 Geode GXLV技術處理器) |
| 300471U | Radial, -55dotc, long life wsitching-power |
| 300CNQ | SCHOTTKY RECTIFIER |
| 300CNQ035 | SCHOTTKY RECTIFIER |
| 300CNQ040 | SCHOTTKY RECTIFIER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 3004430 | 功能描述:DIN導軌式接線端子 UK 5-MTK RoHS:否 制造商:Phoenix Contact 類型:Feed Through Modular Terminal Block 位置/觸點數(shù)量:1 線規(guī)量程:26-14 電流額定值:5 A, 15 A 電壓額定值:300 V, 600 V 安裝風格: 端接類型:Push-In |
| 30044-44L | 制造商:LENOX 功能描述:HOLE SAW BI-METAL 70MM |
| 3004472 | 制造商:Phoenix Contact 功能描述:UK 5-HESI (5X20) |
| 300448 | 功能描述:手工工具 RETAINING PIN RoHS:否 制造商:Molex 產品:Extraction Tools 類型: 描述/功能:Extraction tool |
| 300449 | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:HAND TOOL ASSEMBLY |
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