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參數(shù)資料
| 型號： | 29F800 |
| 廠商： | 意法半導體 |
| 英文描述： | 8 Mbit 1Mb x8 or 512Kb x16, Boot Block Single Supply Flash Memory |
| 中文描述： | 8兆1兆x8或512KB的x16插槽，啟動座單電源閃存 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 142K |
| 代理商： | 29F800 |
M29F800AT, M29F800AB
4/21
Table 3A. M29F800AT Block Addresses
Size
(Kbytes)
(x8)
16
FC000h-FFFFFh
8
FA000h-FBFFFh
8
F8000h-F9FFFh
32
F0000h-F7FFFh
64
E0000h-EFFFFh
64
D0000h-DFFFFh
64
C0000h-CFFFFh
64
B0000h-BFFFFh
64
A0000h-AFFFFh
64
90000h-9FFFFh
64
80000h-8FFFFh
64
70000h-7FFFFh
64
60000h-6FFFFh
64
50000h-5FFFFh
64
40000h-4FFFFh
64
30000h-3FFFFh
64
20000h-2FFFFh
64
10000h-1FFFFh
64
00000h-0FFFFh
Address Range
Address Range
(x16)
7E000h-7FFFFh
7D000h-7DFFFh
7C000h-7CFFFh
78000h-7BFFFh
70000h-77FFFh
68000h-6FFFFh
60000h-67FFFh
58000h-5FFFFh
50000h-57FFFh
48000h-4FFFFh
40000h-47FFFh
38000h-3FFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
00000h-07FFFh
Table 3B. M29F800AB Block Addresses
Size
(Kbytes)
(x8)
64
F0000h-FFFFFh
64
E0000h-EFFFFh
64
D0000h-DFFFFh
64
C0000h-CFFFFh
64
B0000h-BFFFFh
64
A0000h-AFFFFh
64
90000h-9FFFFh
64
80000h-8FFFFh
64
70000h-7FFFFh
64
60000h-6FFFFh
64
50000h-5FFFFh
64
40000h-4FFFFh
64
30000h-3FFFFh
64
20000h-2FFFFh
64
10000h-1FFFFh
32
08000h-0FFFFh
8
06000h-07FFFh
8
04000h-05FFFh
16
00000h-03FFFh
Address Range
Address Range
(x16)
78000h-7FFFFh
70000h-77FFFh
68000h-6FFFFh
60000h-67FFFh
58000h-5FFFFh
50000h-57FFFh
48000h-4FFFFh
40000h-47FFFh
38000h-3FFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
04000h-07FFFh
03000h-03FFFh
02000h-02FFFh
00000h-01FFFh
Chip Enable (E).
The Chip Enable, E, activates
the memory, allowing BusRead and Bus Writeop-
erations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP).
The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
IL
, for at least
t
PLPX
. After Reset/Block Temporary Unprotect
goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or
t
RHEL
, whichever occurs last. See theReady/Busy
Output section, Table 14 and Figure 10, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V
ID
will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
toV
ID
must be slower than
t
PHPHH
.
Ready/Busy Output (RB).
The Ready/Busy pin
is an open-drain outputthat canbe used to identify
when the memory array can be read. Ready/Busy
is high-impedance during Read mode,Auto Select
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impedance. See Table 14 and Figure
10, Reset/Temporary Unprotect AC Characteris-
tics.
During Program or Erase operations Ready/Busy
is Low, V
OL
. Ready/Busy will remain Low during
Read/Reset commands or Hardware Resets until
the memory is ready to enter Read mode.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. ALow will then indicate
that one, or more, of the memories is busy.
Byte/WordOrganizationSelect (BYTE).
The Byte/
Word Organization Select pin is used to switch be-
tween the 8-bit and 16-bit Bus modes of the mem-
ory. When Byte/Word Organization Select is Low,
V
IL
, the memory is in 8-bit mode, when it is High,
V
IH
, the memory is in 16-bit mode.
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