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參數(shù)資料
| 型號： | 29110BJA |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 2K x 8 Asynchronous CMOS Static RAM |
| 中文描述： | 2K X 8 STANDARD SRAM, 70 ns, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 145K |
| 代理商： | 29110BJA |
6
Timing Waveforms
(Continued)
In this write cycle G has control of the output after a period,
TGHQZ. G switching the output to a high impedance state
allows data in to be applied without bus contention after
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are guaran-
teed over temperature. The following rules ensure data
retention:
1. Chip Enable (E) must be held high during data retention;
within V
CC
-0.3V to V
CC
+0.3V.
2. On RAMs which have selects or output enables (e.g., S,
G), one of the selects or output enables should be held in
the deselected state to keep the RAM outputs high im-
pedance, minimizing power dissipation.
3. Inputs which are to be held high (e.g., E) must be kept be-
tween V
CC
+0.3V and 70% of V
CC
during the power up
and down transitions.
4. The RAM can begin operation > 55ns after V
CC
reaches
the minimum operating voltage (4.5V).
(17) TDVWH
(21) TDVEH
(18) TWHDX
(15)
TGHQZ
ADDRESS
G
E
W
Q
D
(10) TAVAX
(22) TAVWH
(14)
TWHAX
(11) TELWH
(12) TAVWL
FIGURE 3. WRITE CYCLE II
(13) TWLWH
V
CC
-0.3V TO V
CC
+0.3V
V
CC
≥
02.0V
4.5V
V
CC
E
4.5V
>55ns
DATA
RETENTION
TIMING
FIGURE 4. DATA RETENTION TIMING
HM-65162
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