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參數(shù)資料
| 型號(hào)： | 29110BJA |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 2K x 8 Asynchronous CMOS Static RAM |
| 中文描述： | 2K X 8 STANDARD SRAM, 70 ns, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 145K |
| 代理商： | 29110BJA |
5
Timing Waveforms
Addresses must remain stable for the duration of the read
cycle. To read, G and E must be
≤
V
IL
and W
≥
V
IH
. The
output buffers can be controlled independently by G while E
is low. To execute consecutive read cycles, E may be tied
low continuously until all desired locations are accessed.
To write, addresses must be stable, E low and W falling low
for a period no shorter than TWLWH. Data in is referenced
with the rising edge of W, (TDVWH and TWHDX). While
addresses are changing, W must be high. When W falls low,
the I/O pins are still in the output state for a period of TWLQZ
and input data of the opposite phase to the outputs must not
be applied, (Bus contention). If E transitions low
simultaneously with the W line transitioning low, or after the
W transition, the output will remain in a high impedance
state. G is held continuously low.
(9) TAVQX
(6) TGLQX
(5) TGLQV
ADDRESS
G
E
Q
(1) TAVAX
(2) TAVQV
(8) TGHQZ
(7) TEHQZ
(3) TELQV
(4) TELQX
FIGURE 1. READ CYCLE
NOTE:
1. W is high for a Read Cycle.
(14) TWHAX
(16) TWLQZ
(21)
TDVEH
(17) TDVWH
(18) TWHDX
ADDRESS
E
W
Q
D
(10) TAVAX
(11) TELWH
(12) TAVWL
(13) TWLWH
(20) TWLEH
(22) TAVWH
FIGURE 2. WRITE CYCLE I
(19) TWHQX
NOTE:
1. G is low throughout Write Cycle.
HM-65162
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