參數(shù)資料
型號(hào): 28F800B5
英文描述: Dual-Slot, PCMCIA Analog Power Controller
中文描述: 智能5引導(dǎo)塊。閃存系列2。 4。 8兆比特
文件頁數(shù): 15/44頁
文件大小: 496K
代理商: 28F800B5
28F400BL-T/B, 28F004BL-T/B
3.1 28F004BL Memory Organization
3.1.1 BLOCKING
The 28F004BL uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block ad-
dress range and the Erase Setup and Erase Confirm
commands are written to the CUl. The 28F004BL is
a random read/write memory, only erasure is per-
formed by block.
3.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow-
er failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being programmed
or erased when RP
Y
is not at 12V. The boot block
can be erased and programmed when RP
Y
is held
at 12V for the duration of the erase or program oper-
ation. This allows customers to change the boot
code when necessary while still providing security
when needed. See the Block Memory Map section
for address locations of the boot block for the
28F004BL-T and 28F004BL-B.
3.1.1.2 Parameter Block Operation
The 28F004BL has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The pa-
rameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. Parameter blocks provide
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices. See the Block Memory Map sec-
tion for address locations of the parameter blocks
for the 28F004BL-T and 28F004BL-B.
3.1.1.3 Main Block Operation
Two main blocks of memory exist on the 28F004BL
(3 x 128-Kbyte blocks and 1 x 96-Kbyte blocks). See
the following section on Block Memory Map for the
address location of these blocks for the 28F004BL-T
and 28F004BL-B.
3.1.2 BLOCK MEMORY MAP
Two versions of the 28F004BL product exist to sup-
port two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F004BL-T
memory map is inverted from the 28F004BL-B mem-
ory map.
3.1.2.1 28F004BL-B Memory Map
The 28F004BL-B device has the 16-Kbyte boot
block located from 00000H to 03FFFH to accommo-
date those microprocessors that boot from the bot-
tom of the address map at 00000H. In the
28F004BL-B the first 8-Kbyte parameter block re-
sides in memory from 04000H to 05FFFH. The sec-
ond 8-Kbyte parameter block resides in memory
space from 06000H to 07FFFH. The 96-Kbyte main
block resides in memory space from 08000H to
1FFFFH. The three 128-Kbyte main blocks reside in
memory space from 20000H to 3FFFFH, 40000H to
5FFFFH and 60000H to 7FFFH. See Figure 10.
7FFFFH
128-Kbyte MAIN BLOCK
5FFFFH
60000H
128-Kbyte MAIN BLOCK
3FFFFH
40000H
128-Kbyte MAIN BLOCK
1FFFFH
20000H
96-Kbyte MAIN BLOCK
07FFFH
08000H
8-Kbyte PARAMETER BLOCK
05FFFH
06000H
8-Kbyte PARAMETER BLOCK
03FFFH
04000H
16-Kbyte BOOT BLOCK
00000H
Figure 10. 28F004BL-B Memory Map
15
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