28F400BL-T/B, 28F004BL-T/B
1.0
PRODUCT FAMILY OVERVIEW
Throughout this datasheet 28F400BL refers to both
the 28F400BL-T and 28F400BL-B devices and
28F004BL refers to both the 28F004BL-T and
28F004BL-B devices. The 4-Mbit flash family refers
to both the 28F400BL and 28F004BL products. This
datasheet comprises the specifications for four sep-
arate products in the 4-Mbit flash family, Section 1
provides an overview of the 4-Mbit flash family in-
cluding applications, pinouts and pin descriptions.
Sections 2 and 3 describe in detail the specific mem-
ory organizations for the 28F400BL and 28F004BL
products respectively, Section 4 combines a de-
scription of the family’s principles of operations. Fi-
nally section 5 describes the family’s operating
specifications.
Product Family
x8/x16 Products
x8-Only Products
28F400BL-T
28F004BL-T
28F400BL-B
28F004BL-B
1.1 Designing for Upgrade to
SmartVoltage Products
Today’s high volume boot block products are up-
gradeable to Intel’s SmartVoltage boot block prod-
ucts that provide program and erase operation at 5V
or 12V V
PP
and read operation at 3V or 5V V
CC
.
Intel’s SmartVoltage boot block products provide the
following enhancements to the boot block products
described in this datasheet:
1. DU pin is replaced by WP
Y
to provide a means to
lock and unlock the boot block with logic signals.
2. 5V Program/Erase operation uses proven pro-
gram and erase techniques with 5V
g
10% ap-
plied to V
PP
.
3. Enhanced circuits optimize performance at 3.3V
V
CC
.
Refer to the 2, 4 or 8Mbit SmartVoltage Boot Block
Flash Memory datasheets for complete specifica-
tions.
When you design with 12V V
PP
boot block products
you should provide the capability in your board de-
sign to upgrade to SmartVoltage products.
Follow these guidelines to ensure compatibility:
1. Connect DU (WP
Y
on SmartVoltage products) to
a control signal or to V
CC
or GND.
2. If adding a switch on V
PP
for write protection,
switch to GND for complete write protection.
3. Allow for connecting 5V to V
PP
and disconnect
12V from the V
PP
line, if desired.
1.2 Main Features
The 28F400BL/28F004BL boot block flash memory
family is a very high performance 4-Mbit (4,194,304
bit) memory family organized as either 256 KWords
(262,144 words) of 16 bits each or 512 Kbytes
(524,288 bytes) of 8 bits each.
Seven Separately Erasable Blocks
including a
Hardware-Lockable boot block
(16,384 Bytes),
two parameter blocks
(8,192 Bytes each) and
four
main blocks
(1 block of 98,304 Bytes and 3 blocks
of 131,072 Bytes) are included on the 4-Mbit family.
An erase operation erases one of the main blocks in
typically 3.4 seconds and the boot or parameter
blocks in typically 2.0 seconds, independent of the
remaining blocks. Each block can be independently
erased and programmed 10,000 times.
The Boot Block
is located at either the top (-T) or
the bottom (-B) of the address map in order to ac-
commodate different microprocessor protocols for
boot code location. The
hardware Iockable boot
block
provides the most secure code storage. The
boot block is intended to store the kernel code re-
quired for booting-up a system. When the RP
Y
pin is
between 11.4V and 12.6V the boot block is unlocked
and program and erase operations can be per-
formed. When the
RP
Y
pin is at or below 4.1V the
boot block is locked and program and erase opera-
tions to the boot block are ignored.
The
ROM/EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package and
the 56-Lead TSOP (Thin Small Outline, 1.2mm thick)
package as shown in Figures 3 and 4, The
28F004BL products are available in the 40-Lead
TSOP (1.2mm thick) package as shown in Figure 5.
28F400BL
products
are
available
in
the
The
Command User Interface (CUI)
serves as the
interface between the microprocessor or microcon-
troller and the internal operation of the 28F400BL
and 28F004BL flash memory products.
Program and Erase Automation
allow program
and erase operations to be executed using a two-
write command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, there-
by unburdening the microprocessor or microcontrol-
ler. Writing of memory data is performed in word or
byte increments for the 28F400BL family and in byte
increments for the 28F004BL family typically within
11
m
s.
3