參數(shù)資料
型號： 28F032C3
英文描述： 3 VOLT ADVANCED+ BOOT BLOCK. 8-. 16-. 32-MBIT FLASH MEMORY FAMILY
中文描述： 3伏高級啟動塊。 8 -. 16 -. 32 - Mbit閃存家庭
文件頁數(shù)： 9/59頁
文件大小： 384K
代理商： 28F032C3
E
3 VOLT ADVANCED+ BOOT BLOCK
9
PRODUCT PREVIEW
Table 2. 3 Volt Advanced+ Boot Block Pin Descriptions
Symbol
Type
Name and Function
A
0
–A
21
INPUT
ADDRESS INPUTS
for memory addresses. Addresses are internally
latched during a program or erase cycle.
8-Mbit x 8 A[0-19], 16-Mbit x 8 A[0-20], 32-Mbit x 8 A[0-21]
8-Mbit x 16 A[0-18], 16-Mbit x 16 A[0-19], 32-Mbit x 16 A[0-20]
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, configuration and status register data.
The data pins float to tri-state when the chip is de-selected or the outputs
are disabled.
DQ
0
–DQ
7
INPUT/OUTPUT
DQ
8
–DQ
15
INPUT/OUTPUT
DATA INPUTS/OUTPUTS:
Inputs array data on the second CE# and
WE# cycle during a Program command. Data is internally latched.
Outputs array and configuration data. The data pins float to tri-state when
the chip is de-selected.
Not included on x8 products.
CE#
INPUT
CHIP ENABLE:
Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels.
OE#
INPUT
OUTPUT ENABLE:
Enables the device’s outputs through the data
buffers during a read operation. OE# is active low.
WE#
INPUT
WRITE ENABLE:
Controls writes to the Command Register and
memory array. WE# is active low. Addresses and data are latched on
the rising edge of the second WE# pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN:
Uses two voltage levels (V
IL
, V
IH
) to
control reset/deep power-down mode.
When RP# is at logic low, the device is in reset/deep power-down
mode
, which drives the outputs to High-Z, resets the Write State
Machine, and minimizes current levels (I
CCD
).
When RP# is at logic high, the device is in standard operation
.
When RP# transitions from logic-low to logic-high, the device resets all
blocks to locked and defaults to the read array mode.
WP#
INPUT
WRITE PROTECT:
Controls the lock-down function of the flexible
Locking feature
When WP# is a logic low, the lock-down mechanism is enabled
and
blocks marked lock-down cannot be unlocked through software.
When WP# is logic high, the lock-down mechanism is disabled
and
blocks previously locked-down are now locked and can be unlocked and
locked through software. After WP# goes low, any blocks previously
marked lock-down revert to that state.
See Section 3.3 for details on block locking.
V
CC
SUPPLY
DEVICE POWER SUPPLY:
[2.7 V–3.6 V] Supplies power for device
operations.
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