參數(shù)資料
型號: 28F001BX
廠商: Intel Corp.
英文描述: 5 V Boot Block Flash Memory(5 V引導(dǎo)塊閃速存儲器)
中文描述: 5伏啟動塊閃存(5伏引導(dǎo)塊閃速存儲器)
文件頁數(shù): 16/39頁
文件大?。?/td> 648K
代理商: 28F001BX
28F001BX
E
16
At this point, a Read Array command can be written
to the command register to read data from blocks
other than that which is suspended
. The only
other valid commands at this time are Read Status
Register (70H) and Erase Resume (D0H), at which
time the WSM will continue with the erase
sequence. The erase suspend status and WSM
status bits of the status register will be cleared.
After the Erase Resume command is written to it,
the 28F001BX automatically outputs status register
data when read (see Figure 10, 28F001BX Erase
Suspend/ Resume Flowchart).
Table 4. 28F001BX Status Register Definitions
WSMS
ESS
ES
PS
VPPS
R
R
R
7
6
5
4
3
2
1
0
SR.7
1
0
=
=
=
WRITE STATE MACHINE STATUS
Ready
Busy
NOTES:
The WSM status bit must first be checked to
determine program or erase completion, before the
program or erase status bits are checked for success.
SR.6
1
0
=
=
=
ERASE SUSPEND STATUS
Erase Suspended
Erase in Progress/Completed
If the program
and
erase status bits are set to
“1s”
during an erase attempt, an improper command
sequence was entered. Attempt the operation again.
SR.5
1
0
=
=
=
ERASE STATUS
Error in Block Erasure
Successful Block Erase
If V
PP
low status is detected, the status register must
be cleared before another program or erase operation
is attempted.
SR.4
1
0
=
=
=
PROGRAM STATUS
Error in Byte Program
Successful Byte Program
The V
PP
status bit, unlike an A/D converter, does not
provide continuous indication of V
PP
level. The WSM
interrogates the V
PP
level only after the Program or
Erase command sequences have been entered and
informs the system if V
PP
has not been switched on.
The V
PP
status bit is not guaranteed to report
accurate feedback between V
PPL
and V
PPH
.
SR.3
1
0
=
=
=
V
PP
STATUS
V
PP
Low Detect; Operation Abort
V
PP
OK
SR.2–SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS
These bits are reserved for future use and should be
masked out when polling the status register.
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