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參數(shù)資料
| 型號(hào)： | 28F001BX |
| 廠商： | Intel Corp. |
| 英文描述： | 5 V Boot Block Flash Memory(5 V引導(dǎo)塊閃速存儲(chǔ)器) |
| 中文描述： | 5伏啟動(dòng)塊閃存（5伏引導(dǎo)塊閃速存儲(chǔ)器） |
| 文件頁數(shù)： | 12/39頁 |
| 文件大?。?/td> | 648K |
| 代理商： | 28F001BX |
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28F001BX
E
12
3.1
Read
The 28F001BX has three read modes. The memory
can be read from any of its blocks, and information
can be read from the intelligent identifier or the
status register. V
PP
can be at either V
PPL
or V
PPH
.
The first task is to write the appropriate Read Mode
command to the command register (array,
intelligent identifier, or status register). The
28F001BX automatically resets to read array mode
upon initial device power-up or after exit from deep
power-down. The 28F001BX has four control pins,
two of which must be logically active to obtain data
at the outputs. Chip Enable (CE#) is the device
selection control, and when active enables the
selected memory device. Output Enable (OE#) is
the data input/output (DQ
0
–DQ
7
) direction control,
and when active drives data from the selected
memory onto the I/O bus. RP# and WE# must also
be at V
IH
. Figure 11 illustrates read bus cycle
waveforms.
3.2
Output Disable
With OE# at a logic-high level (V
IH
), the device
outputs are disabled. Output pins (DQ
0
–DQ
7
) are
placed in a high-impedance state.
3.3
Standby
CE# at a logic-high level (V
) places the 28F001BX
in standby mode. Standby operation disables much
of the 28F001BX’s circuitry and substantially
reduces device power consumption. The outputs
(DQ
0
–DQ
7
) are placed in a high-impedance state
independent of the status of OE#. If the 28F001BX
is deselected during erase or program, the device
will continue functioning and consuming normal
active power until the operation is completed.
Table 2. 28F001BX Bus Operations
Mode
Notes
RP#
CE#
OE#
WE#
A
9
A
0
V
PP
DQ
0
–7
Read
1, 2, 3
V
IH
V
IL
V
IL
V
IH
X
X
X
D
OUT
Output Disable
2
V
IH
V
IL
V
IH
V
IH
X
X
X
High Z
Standby
2
V
IH
V
IH
X
X
X
X
X
High Z
Deep Power Down
2
V
IL
X
X
X
X
X
X
High Z
Intelligent Identifier
(Mfr)
2, 3, 4
V
IH
V
IL
V
IL
V
IH
V
ID
V
IL
X
89H
Intelligent Identifier
(Device)
2, 3, 4, 5
V
IH
V
IL
V
IL
V
IH
V
ID
V
IH
X
94H,
95H
Write
2, 6, 7, 8
V
IH
V
IL
V
IH
V
IL
X
X
X
D
IN
NOTES:
1.
Refer to Section 10.4, DC Characteristics When V
PP
= V
PPL
, memory contents can be read but not programmed or
erased.
X can be V
IL
or V
IH
for control pins and addresses, and V
PPL
or V
PPH
for V
PP
.
See DC Characteristics for V
PPL
, V
PPH
, V
HH
and V
ID
voltages.
Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. A
1
–A
8
,
A
10
–A
16
= V
IL
.
Device ID = 94H for the 28F001BX-T and 95H for the 28F001BX-B.
Command writes involving block erase or byte program are successfully executed only when V
PP
= V
PPH
.
Refer to Table 3 for valid D
IN
during a write operation.
Program or erase the boot block by holding RP# at V
HH
or toggling OE# to V
HH
. See AC waveforms for program/erase
operations.
2.
3.
4.
5.
6.
7.
8.
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| 28F002BC | 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F001BX-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 28F001BX-T | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY |
| 28F001BX-T/28F001BX-B/28F001BN-T/BN-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/28F001BX-B/28F001BN-T/BN-B |
| 28F001BX-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:28F001BX-T/B |
| 28F002BC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY |
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