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參數(shù)資料
| 型號： | 22C10 |
| 英文描述： | 256-Bit Nonvolatile CMOS Static RAM |
| 中文描述： | 256位非易失性的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 70K |
| 代理商： | 22C10 |
CAT22C10
8
Doc. No. 25018-0A 2/98 N-1
Recall
At anytime, except during a store operation, taking the
RECALL
pin low will initiate a recall operation. This is
independent of the state of
CS
,
WE
, or A
0
–A
5
. After the
RECALL
pin has been held low for the duration of the
Recall Pulse Width (t
RCP
), the recall will continue inde-
pendent of any other inputs. During the recall, the entire
contents of the E
2
PROM array is transferred to the Static
RAM array. The first byte of data may be externally
accessed after the recalled data access time from end of
recall (t
ARC
) is met. After this, any other byte may be
accessed by using the normal read mode.
If the
RECALL
pin is held low for the entire Recall Cycle
time (t
RCC
), the contents of the Static RAM may be
immediately accessed by using the normal read mode.
A recall operation can be performed an unlimited num-
ber of times without affecting the integrity of the data.
The outputs I/O
0
–I/O
3
will go into the high impedance
state as long as the
RECALL
signal is held low.
Store
At any time, except during a recall operation, taking the
STORE
pin low will initiate a store operation. This takes
place independent of the state of
CS
,
WE
or A
0
–A
5
. The
STORE
pin must be held low for the duration of the Store
Pulse Width (t
STP
) to ensure that a store operation is
initiated. Once initiated, the
STORE
pin becomes a
“Don’t Care”, and the store operation will complete its
transfer of the entire contents of the Static RAM array
into the E
2
PROM array within the Store Cycle time
(t
STC
). If a store operation is initiated during a write cycle,
the contents of the addressed Static RAM byte and its
corresponding byte in the E
2
PROM array will be un-
known.
During the store operation, the outputs are in a high
impedance state. A minimum of 100,000 store opera-
tions can be performed reliably and the data written into
the E
2
PROM array has a minimum data retention time
of 10 years.
DATA PROTECTION DURING POWER-UP AND
POWER-DOWN
The CAT22C10 has on-chip circuitry which will prevent
a store operation from occurring when V
CC
falls below
3.0V typ. This function eliminates the potential hazard of
spurious signals initiating a store operation when the
system power is below 3.0V typ.
Figure 4. Recall Cycle Timing
5153 FHD F08
5153 FHD F07
Figure 5. Store Cycle Timing
CS
DATA I/O
RECALL
ADDRESS
DATA UNDEFINED
DATA VALID
HIGH-Z
tRCZ
tORC
tARC
tRCP
tRCC
STORE
DATA I/O
tSTZ
tOST
HIGH-Z
tSTP
tSTC
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