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| 型號(hào)： | 21628 |
| 英文描述： | 1.8 Volt-only Flash Memory Technology |
| 中文描述： | 1.8伏只快閃記憶體技術(shù) |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大小： | 75K |
| 代理商： | 21628 |
6
1.8 Volt-only Flash Memory Technology Background
accomplished through a unique bit sensing circuit in conjunction with a proprietary,
intelligent programming algorithm. Together they exploit the fact that at the location selected
for programming, only the bits to be programmed with a logic “0” require programming
current (the other bits are already at logic “1” from a previous erase operation). Managing the
current makes this approach silicon efficient, while maintaining overall programming
performance.
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The erase operation removes electrons (charge) from the cell’s floating gate. In AMD devices
Fowler-Nordheim tunneling (FN) is the mechanism employed. FN tunneling is a quantum
mechanical process whose explanation is beyond the scope of this paper. Understanding the
constraints this mechanism places on the design is our interest here. FN tunneling requires an
electric field across the tunneling oxide. The strength of this field for a given oxide thickness
determines the erase performance. Again, reducing the external supply voltage while
maintaining performance presents yet another challenge.
AMD pioneered its patented Negative Gate Erase (NGE) technique several years ago as a
solution to the problem of maintaining erase performance without requiring multiple external
voltage sources. The NGE technique has proven to be a key enabler of AMD’s ability to offer
first 5 volt-only followed by 2.7 volt-only, 2.2 volt-only, and now 1.8 volt-only devices. NGE
takes advantage of the superposition principle of electric fields. Applying a negative bias to
the control gate and a small positive bias to the source generates the resultant field intensity
required for FN tunneling (see Figure 3). The key here is the current reduction as a result of
reducing the source voltage. Keeping the source voltage low suppresses avalanche-dominated
conduction between the source and the substrate, reducing overall internal power generating
requirements. NGE therefore allows a charge pump approach to be utilized with negligible
impact on die size, while maintaining erase performance.
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