
MMX Instruction Set
59
20726D/0—January 2000
AMD-K6 MMX Enhanced Processor Multimedia Technology
Preliminary Information
PMADDWD
mnemonic
opcode
description
PMADDWD mmreg1, mmreg2/mem64 0F F5h
Multiply signed packed 16-bit values and add the 32-bit
results
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
none
MMX
none
The PMADDWD instruction multiplies signed 16-bit values from the source operand
(an MMX register or a 64-bit memory location) by the corresponding signed 16-bit
values in the destination operand (an MMX register), adds the resulting 32-bit values
from the left and right halves of the 64-bit work space, and stores the 32-bit sums in
the MMX destination register.
Note:
If all four of the 16-bit operands are 8000h, the result wraps around to 8000_0000h
because the maximum negative 16-bit value of 8000h multiplied by itself equals
4000_0000h, and 4000_0000h added to 4000_0000h equals 8000_0000h. The result
of multiplying two negative numbers should be a positive number, but 8000_0000h
is the maximum possible 32-bit negative number rather than a positive number.
This is the only instance of wraparound that can occur as a result of the
PMADDWD instruction.
Exception
Invalid opcode (6)
Device not available (7)
Real
X
X
Virtual
8086
X
X
Protected Description
X
X
The emulate MMX instruction bit (EM) of the control register (CR0) is set to 1.
Save the floating-point or MMX state if the task switch bit (TS) of the control
register (CR0) is set to 1.
During instruction execution, the stack segment limit was exceeded.
During instruction execution, the effective address of one of the segment
registers used for the operand points to an illegal memory location.
One of the instruction data operands falls outside the address range 00000h
to 0FFFFh.
A page fault resulted from the execution of the instruction.
An exception is pending due to the floating-point execution unit.
Stack exception (12)
General protection (13)
X
X
Segment overrun (13)
X
X
Page fault (14)
Floating-point exception
pending (16)
Alignment check (17)
X
X
X
X
X
X
X
An unaligned memory reference resulted from the instruction execution,
and the alignment mask bit (AM) of the control register (CR0) is set to 1.
(In Protected Mode, CPL = 3.)