
MMX Instruction Set
45
20726D/0—January 2000
AMD-K6 MMX Enhanced Processor Multimedia Technology
Preliminary Information
PANDN
mnemonic
opcode
description
PANDN mmreg1, mmreg2/mem64 0F DFh
Invert a 64-bit value, then AND the inverted value and a 64-bit
value in memory or an MMX register
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
none
MMX
none
The PANDN instruction first operates on the 64-bit destination operand (an MMX
register) to complete a bitwise logical NOT, inverting each bit. This operation changes
1 bits to 0 bits and 0 bits to 1 bits, storing the results in the destination operand. The
inverted 64-
bit destination operand is then logically AND’d with the 64-bit source
operand (an MMX register or a 64-bit memory operand) to complete the PANDN
operation.
If corresponding bits in the source operand and the inverted destination operand are
both 1, the resulting bit is 1 in the destination. If either bit in the source operand or
the inverted destination operand is 0, the resulting bit is 0 in the destination.
The PANDN instruction can be used to extract alternate operands from packed fields
based on the inverse of the masks that are produced by the compare instructions—
PCMPEQ and PCMPGT. This technique can eliminate branch prediction overhead in
MMX routines.
Exception
Invalid opcode (6)
Device not available (7)
Real
X
X
Virtual
8086
X
X
Protected Description
X
X
The emulate MMX instruction bit (EM) of the control register (CR0) is set to 1.
Save the floating-point or MMX state if the task switch bit (TS) of the control
register (CR0) is set to 1.
During instruction execution, the stack segment limit was exceeded.
During instruction execution, the effective address of one of the segment
registers used for the operand points to an illegal memory location.
One of the instruction data operands falls outside the address range 00000h
to 0FFFFh.
A page fault resulted from the execution of the instruction.
An exception is pending due to the floating-point execution unit.
Stack exception (12)
General protection (13)
X
X
Segment overrun (13)
X
X
Page fault (14)
Floating-point exception
pending (16)
Alignment check (17)
X
X
X
X
X
X
X
An unaligned memory reference resulted from the instruction execution,
and the alignment mask bit (AM) of the control register (CR0) is set to 1.
(In Protected Mode, CPL = 3.)