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26
MMX Instruction Set
AMD-K6 MMX Enhanced Processor Multimedia Technology
20726D/0—January 2000
Preliminary Information
PACKUSWB
mnemonic
opcode
description
PACKUSWB mmreg1, mmreg2/mem64 0F 67h
Pack with saturation signed16-bit operands into unsigned
8-bit results
Privilege:
Registers Affected:
Flags Affected:
Exceptions Generated:
none
MMX
none
The PACKUSWB instruction performs a pack and saturate operation on four signed
16-bit values in the first operand and four signed 16-bit values in the second operand.
The eight unsigned 8-bit results are placed in the specified MMX register.
The pack operation is a data conversion. The PACKUSWB instruction converts or
packs the eight signed 16-bit values into eight unsigned 8-bit values, applying
saturating arithmetic. If the signed 16-bit value is a negative number, it saturates to 0
(00h). If the signed 16-bit value is greater than 255 (FFh), it saturates to 255 (FFh). All
values between 0 and 255 are represented with their unsigned 8-bit value.
The first operand must be an MMX register. In addition to providing the first operand,
this MMX register is the location where the result of the pack and saturate operation
is stored. The second operand can be an MMX register or a 64-bit memory location.
Exception
Invalid opcode (6)
Device not available (7)
Real
X
X
Virtual
8086
X
X
Protected Description
X
X
The emulate MMX instruction bit (EM) of the control register (CR0) is set to 1.
Save the floating-point or MMX state if the task switch bit (TS) of the control
register (CR0) is set to 1.
During instruction execution, the stack segment limit was exceeded.
During instruction execution, the effective address of one of the segment
registers used for the operand points to an illegal memory location.
One of the instruction data operands falls outside the address range 00000h
to 0FFFFh.
A page fault resulted from the execution of the instruction.
An exception is pending due to the floating-point execution unit.
Stack exception (12)
General protection (13)
X
X
Segment overrun (13)
X
X
Page fault (14)
Floating-point exception
pending (16)
Alignment check (17)
X
X
X
X
X
X
X
An unaligned memory reference resulted from the instruction execution,
and the alignment mask bit (AM) of the control register (CR0) is set to 1.
(In Protected Mode, CPL = 3.)