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| 型號： | 20575 |
| 英文描述： | Wireless LAN DSSS PC Card Reference Design Application ? 220KB (PDF) |
| 中文描述： | 無線局域網擴頻PC卡參考設計中的應用？欺詐郵件（PDF格式） |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 220K |
| 代理商： | 20575 |
5
PIN CONNECTIONS
The pin connections among the Am79C930 device, the
HARRIS PRISM chipset, Flash memory, SRAM and
oscillator are given in Table 1.
Note:
different from the pin connections that would be used
for an ISA Plug and Play design. This application note
covers only the PC CARD case.
The pin connections for a PC CARD design are
Table 1.
Am79C930 Pin Connections
AMD
Am79C930
Pin Name
USER2
Pin
No.
I/O
I/O
AMD Am 79C930
Pin Function
API
will determine signal
timing
API will determine signal
timing
API will determine signal
timing
5-V supply (VCC)
802.11 HARRIS DS PHY PC
CARD System Connections
NC
I/O
802.11 HARRIS DS
PHY PC CARD
System Function
1
I
USER3
2
O
Radio to Power Enable
Radio Power Enable
USER4
3
O
HFA3524 to SYNTH.LE (Pin
13)
5-V supply
I
Synthesizer serial bus
latch enable
VDDM
4, 16,
29
5
I
XCE
O
Chip enable for extra
peripheral on memory
bus
Address bus for memory
devices
NC
MA[16:0]
O
MA[16:0] to FLASH.A[16:0]
I
Address bus for
FLASH device
Address bus for
SRAM device
MA[14:0] to SRAM.A[14:0]
I
VSSM
7, 21,
32
11
I
GND
GND
MWE
O
Write enable for memory
devices
FLASH.WE
I
Write enable for
FLASH device
Write enable for
SRAM device
SRAM.WE
I
VCC
MD[7:0]
17, 89 I
3.5-V supply (VCC)
Data bus for memory
devices
3.5-V supply
FLASH.D[7:0]
I/O
I/O
Data bus for FLASH
device
Data bus for SRAM
device
Output enable for
FLASH device
Output enable for
SRAM device
Chip enable for
SRAM device
Chip enable for
FLASH device
Data bus for PC
CARD
SRAM.D[7:0]
I/O
MOE
38
O
Output enable for
memory devices
FLASH.OE
I
SRAM.OE
I
SCE
39
O
Chip enable for SRAM
device
Chip enable for FLASH
device
Data bus for PC CARD
SRAM.CE
I
FCE
40
O
FLASH.CE
I
D[7:0]
I/O
PC CARD.D[7:0]
I/O
VSSP
STSCHG
44, 76 I
45
GND
PC CARD STSCHG
function
GND
NC (PC CARD optional - not
used in this implementation)
O
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