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| 型號： | 20575 |
| 英文描述： | Wireless LAN DSSS PC Card Reference Design Application ? 220KB (PDF) |
| 中文描述： | 無線局域網(wǎng)擴(kuò)頻PC卡參考設(shè)計(jì)中的應(yīng)用？欺詐郵件（PDF格式） |
| 文件頁數(shù)： | 19/25頁 |
| 文件大?。?/td> | 220K |
| 代理商： | 20575 |
18
ware must modify certain bit fields of the MAC
header which the device driver is unable to fill in at
the time of creation). The internal descriptor contains
a pointer which points to the SRAM location that con-
tains the MSDU data that has been passed from the
device driver. If fragmentation is required, then mul-
tiple internal descriptors are created, each contain-
ing a PLCP header and a MAC header for one
fragment, and each pointing to a portion of the
MSDU data that has been passed from the device
driver. The “internal descriptor” structures are not
shared with the device driver. The device driver is
unaware that such descriptors have been created.
The purpose of the internal descriptors is to allow
for fragmentation, if needed, and to create a location
to store the appropriately formed PLCP headers and
modified MAC headers.
Note:
The Am79C930 device firmware will compute the
CRC16 for the PHY PLCP i.e., this operation is not performed
in hardware. The irmware CRC16 operation consists of a few
lookups into a small lookup table. Therefore, the firmware
implementation is quite simple and fast.
3. The Am79C930 firmware monitors CHBSY (CHBSY
is supplied by the PHY through the USER5/EXTCH-
BSY input). The CHBSY signal is available to
Am79C930 firmware as a direct read of a register
bit. Changes to the CCA signal value are signaled
to firmware through interrupts to the embedded
80188 core of the Am79C930 device, or they are
seen as the CHBSY bit is polled, depending upon
which firmware procedure is examining the CHBSY
status.
4. When the Am79C930 device firmware sees
CHBSY=0 (medium IDLE) for the required DIFS time
plus the selected backoff time, then the firmware ini-
tiates the TX operation by asserting the TXS bit of
TIR8.
5. TXCMD - TX_PEB is asserted under state machine
control in response to the assertion of the TXS bit of
TIR8.
6. TXPE - TX_PEA is asserted under state machine
control after a programmable number of bit times.
(The programmable delay time was set during
Am79C930 configuration, as part of an API call.)
7. TXDATA - TXD provides data from the TX FIFO after
a programmable time following the assertion of
TXPE - TX_PEA. (The programmable delay time
was set during Am79C930 configuration, as part of
an API call.)
8. The SFD DETECT logic inside of the Am79C930
device is programmed to recognize the Unique
Word for outgoing transmissions. When the Unique
Word is detected, the Am79C930 device will wait
the programmed PFL time (TCR3[3:0]) and then
begin CRC32 calculation. At the same time that the
CRC32 logic is started, the device will switch clock
rates to allow for a dynamic rate change of the
frame, if needed. The dynamic rate change will
occur if the dynamic rate bit (TIR8[3] has been set.
If the bit has been set, then the preamble, Unique
Word and PLCP header fields will leave the
Am79C930 device at a 1 Mbps rate, and the MAC
header and the remainder of the frame will leave
the Am79C930 device at a 2 Mbps rate.
9. At the end of the data portion of the TX, the TXDATA
pin of the Am79C930 device returns to its default state.
10.After a programmable delay, the TXPE (TX_PEA) pin
will become deasserted.
11.After another programmable delay, the TXCMD -
TX_PEB pin is deasserted, ending the transmission.
Interface Timing
The following timing diagrams indicate the logical signal-
ling that will be generated between the HARRIS DS PHY
chipset and the Am79C930 device for various operations.
Initialization to Receive (RX)
See Figure 4 for the initialization-to-receive timing dia-
gram.
Receive to Transmit to Receive (RX to TX to RX)
See Figure 5 for the receive-to-transmit-to-receive timing
diagram.
Receive (RX) to Sleep
For the SLEEP mode of the HSP3824 and the other
devices of the HARRIS HFA3x24 to be placed into the
sleep mode, the following signals should be placed into
the states shown in Table 7.
Table 7.
Pin Name: AMD_NAME
(HARRIS_NAME)
TXCMD (TX_PEB)
TXPE (TX_PEA)
RXPE (RX_PE)
SLEEP Mode Signal States
Pin State During
Sleep Mode
0
0
0
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