- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371361 > 20575 Wireless LAN DSSS PC Card Reference Design Application ? 220KB (PDF) PDF資料下載
參數(shù)資料
| 型號(hào)： | 20575 |
| 英文描述： | Wireless LAN DSSS PC Card Reference Design Application ? 220KB (PDF) |
| 中文描述： | 無線局域網(wǎng)擴(kuò)頻PC卡參考設(shè)計(jì)中的應(yīng)用？欺詐郵件（PDF格式） |
| 文件頁數(shù)： | 18/25頁 |
| 文件大小： | 220K |
| 代理商： | 20575 |
17
Am79C930 Register Settings Summary
Table 6 indicates the required configuration register set-
tings for the Am79C930 device, when combined in a de-
sign with the HARRIS PRISM chip on a PC CARD card.
Host PC/Adapter Card Interaction
Normal system operation (i.e., transmission and recep-
tion of frames) is controlled through the use of a soft-
ware device driver. The device driver will interface with
the Am79C930 device through command, status, and
data structures that exist in the SRAM component of the
system and through registers that are part of the
Am79C930 device. The Am79C930 device, in turn, will
perform all interface functions that are required in order
to operate the remaining system components (i.e., the
HARRIS PRISM chipset).
TX Flow
The Am79C930 device will perform the following func-
tions of the TX operation:
I
Monitor CCA input for TX defer procedure; execute
backoff if necessary
I
Execute TX power ramp-up sequence for radio
when defer=FALSE and a TX frame is queued
I
Generate preamble (uses DMA to transfer to TX
FIFO)
I
Generate Unique Word (uses DMA to transfer to TX
FIFO)
I
Generate PLCP header (uses DMA to transfer to TX
FIFO)
I
Generate PLCP CRC16 value (uses DMA to trans-
fer to TX FIFO)
I
Dynamic rate switch from 1 Mbps to 2 Mbps (if
necessary)
I
Generate MAC header (uses DMA transfer to TX
FIFO)
I
Generate MAC data (uses DMA to transfer to TX
FIFO)
I
Generate MAC CRC32 (generated by TX hardware
state machine)
I
Execute TX power ramp-down sequence for radio
(by TX hardware state machine control)
The transmit operation is initiated by a request from the
software driver to the Am79C930-based adapter card.
The driver will first place the data to be transmitted into
a predefined TX buffer area of the SRAM. The firmware
will poll the TX descriptors at a periodic interval. At the
next poll of the TX descriptors, the firmware will discover
the new TX frame and will initiate the MAC TX Sequence
as follows.
TX SEQUENCE for the Am79C930 Device Generates
and Strips PHY Fields
Note:
Only the interaction between the Am79C930 de-
vice and the HARRIS PRISM subsystem is described.
The mode of operation selected for the Am79C930/
HARRIS PRISM chip application is one in which the
Am79C930 device will generate preamble, Unique
Word, and PLCP header for transmission, for an RX
frame, the Am79C930 device will remove these fields.
As such, the first operation for the Am79C930 device in
response to the discovery of a TX frame waiting in the
TX descriptor is to prepare the necessary PPDU(s) from
the MSDU. This step and those that follow in sequence
are described below.
1. The Am79C930 firmware has prepared ahead and
already has enabled the DMA0 engine to move the
preamble plus Unique Word (UW) from a template
in SRAM into the TX FIFO. Effectively, these fields
have been preloaded into the TX FIFO, even before
the device driver has written a descriptor for a trans-
mit frame.
2. The Am79C930 firmware determines whether the
MSDU should be fragmented. If no fragmentation is
needed, then the firmware creates a single “internal
descriptor” which contains the appropriately formed
PLCP header, including a calculated CRC16, and
an appropriately formed MAC header (which was
created by the device driver and passed to the firm-
ware as part of the MSDU “data.” However, the firm-
Table 6.
Am79C930 Register Settings
Am79C930
Register
MIR8
Required Configuration Setting
08h - 0 wait state FLASH
09h - 1 wait state FLASH
0Ah - 2 wait state FLASH
0Bh - 3 wait state FLASH
82h - 0 wait state SRAM
92h - 1 wait state SRAM
write to this register after all other regis-
ters have been configured because the
MIR9[1]=1 setting will prevent writes to
some of the configuration registers
40h
00h
08h
02h
don’t care
A0h
F3h
FFh
D8h
82h
83h
20h
89h
MIR9
TIR2
TIR11
TIR26
TCR7
TCR8
TCR9
TCR10
TCR13
TCR14
TCR15
TCR27
TCR28
TCR30
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 20602 | 3.0 Volt-only Flash Memory Technology |
| 206043-1 | EINBAUKUPPLUNG FLANSCH 14POL GROESSE 11 |
| 206043-3 | KUPPLUNG AUSSENGEWINDE 14POL GROESSE 17 |
| 206062-1 | CONNECTORS CIRCULAR |
| 206136-1 | KUPPLUNGSGEHAEUSE 7POL GEHAEUSE 23 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 2057-500 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 2057500-1 | 制造商:TE Connectivity / AMP 功能描述: |
| 2057-5016-78 | 制造商:Omnivision Technologies Inc 功能描述: |
| 2057-5119-02 | 功能描述:RF 連接器 PCB PLUG SEALED RoHS:否 制造商:Bomar Interconnect 產(chǎn)品:Connectors 射頻系列:BNC 型式:Jack (Female) 極性: 觸點(diǎn)電鍍:Gold 阻抗: 端接類型:Solder 主體類型:Straight Bulkhead 電纜類型: |
| 2057555-1 | 功能描述:I/O 連接器 SFP+ ENHANCED 1X2 CA GE ASSEMBY RoHS:否 制造商:Hirose Connector 產(chǎn)品:Plugs 系列:DH 端口數(shù)量: 位置/觸點(diǎn)數(shù)量:51 節(jié)距:1 mm 觸點(diǎn)電鍍: 觸點(diǎn)材料: 型式:Male 電流額定值:0.5 A 安裝風(fēng)格:Cable 端接類型:IDC 顏色: 安裝角: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。