(PS) ÷10 or ÷30 Processor Clock Divider 1 2 ... 64 " />
參數(shù)資料
型號: 20-101-0732
廠商: Rabbit Semiconductor
文件頁數(shù): 71/126頁
文件大小: 0K
描述: INTERFACE SMART SCREEN OP7100
標準包裝: 1
系列: SBC
模塊/板類型: 單板計算機模塊
適用于相關(guān)產(chǎn)品: OP7100
其它名稱: 20-101-732
20-101-732-ND
OP7100
Hardware
49
Prescaler
(PS)
÷10
or
÷30
Processor
Clock
Divider
1
2
...
64
Divide
Ratio
(DR)
16
or
64
External
Clock
The prescaler (PS), the divide ratio (DR), and the SS bits form a baud-rate
generator, as shown in Figure 3-23.
Figure 3-23. Z180 Baud-Rate Generator
DR (Divide Ratio)
This bit controls one stage of frequency division in the baud-rate generator.
If 1 then divide by 64. If 0 then divide by 16. This is the only control bit
that affects the external clock frequency.
PEO (Parity Even/Odd)
This bit affects parity: 0
even parity, 1 odd parity. It is effective only
if MOD1 is set in CNTLA (parity enabled).
/CTS/PS (Clear to Send/Prescaler)
When read, this bit gives the state of external pin /CTS: 0
low,
1
high. When /CTS is high, RDRF is inhibited so that incoming receive
characters are ignored. When written, this bit has an entirely different
function. If a 0 is written, the baud-rate prescaler is set to divide by 10. If a
1 is written, it is set to divide by 30.
MP (Multiprocessor Mode)
When this bit is set to 1, the multiprocessor mode is enabled. The multi-
processor bit (MPB) is included in transmitted data as shown here.
start bit, data bits, MPB, stop bits
The MPB is 1 when MPBT is 1 and 0 when MPBT is 0.
MPBT (Multiprocessor Bit Transmit)
This bit controls the multiprocessor bit (MPB). When MPB is 1, transmit-
ted bytes will get the attention of other units listening only for bytes with
MPB set.
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