參數(shù)資料
型號: 20-101-0732
廠商: Rabbit Semiconductor
文件頁數(shù): 70/126頁
文件大?。?/td> 0K
描述: INTERFACE SMART SCREEN OP7100
標(biāo)準(zhǔn)包裝: 1
系列: SBC
模塊/板類型: 單板計(jì)算機(jī)模塊
適用于相關(guān)產(chǎn)品: OP7100
其它名稱: 20-101-732
20-101-732-ND
OP7100
48
Hardware
RE (Receiver Enable)
This bit controls the receiver: 1
enabled, 0 disabled. When this bit is
cleared, the processor aborts the operation in progress, but does not disturb
RDRF or the error flags.
MPE (Multiprocessor Enable)
This bit (1
enabled, 0 disabled) controls multiprocessor communica-
tion mode which uses an extra bit for selective communication when a
number of processors share a common serial bus. This bit has effect only
when MP in Control Register B is set to 1. When this bit is 1, only bytes
with the MP bit on will be detected. Others are ignored. If this bit is 0, all
bytes received are processed. Ignored bytes do not affect the error flags or
RDRF.
ASCI Control Register B
Control Register B configures the multiprocessor mode, parity, and baud
rate for each channel.
SS (Source/Speed Select)
Coupled with the prescaler (PS) and the divide ratio (DR), the SS bits select
the source (internal or external clock) and the baud rate divider, as shown
in Table 3-4.
CNTLB0
(02H) and CNTLB1 (03H)
7654
3210
MPBT
MP
/CTS
PS
PEO
DR
SS2
SS1
SS0
R / W
Table 3-4. Baud Rate Divide Ratios
for Source/Speed Select Bits
SS2
SS1
SS0
Divide Ratio
00
0
÷ 1
00
1
÷ 2
01
0
÷ 4
01
1
÷ 8
10
0
÷ 16
10
1
÷ 32
11
0
÷ 64
1
external clock*
*
May not exceed system clock ÷ 40
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