參數(shù)資料
型號: 20-101-0732
廠商: Rabbit Semiconductor
文件頁數(shù): 6/126頁
文件大?。?/td> 0K
描述: INTERFACE SMART SCREEN OP7100
標(biāo)準(zhǔn)包裝: 1
系列: SBC
模塊/板類型: 單板計算機模塊
適用于相關(guān)產(chǎn)品: OP7100
其它名稱: 20-101-732
20-101-732-ND
OP7100
Memory, I/O Map, and Interrupt Vectors
103
Table C-2. Z180 Internal I/O Registers Addresses 0x00–0x3F (concluded)
Address
Name
Description
0x18
FRC
Free-running counter
0x19–0x1F
Reserved
0x20
SAR0L
DMA source address Channel 0, least
0x21
SAR0H
DMA source address Channel 0, most
0x22
SAR0B
DMA source address Channel 0, extra bits
0x23
DAR0L
DMA destination address Channel 0, least
0x24
DAR0H
DMA destination address Channel 0, most
0x25
DAR0B
DMA destination address Channel 0, extra bits
0x26
BCR0L
DMA Byte Count Register Channel 0, least
0x27
BCR0H
DMA Byte Count Register Channel 0, most
0x28
MAR1L
DMA Memory Address Register Channel 1, least
0x29
MAR1H
DMA Memory Address Register Channel 1, most
0x2A
MAR1B
DMA Memory Address Register Channel 1, extra
bits
0x2B
IAR1L
DMA I/O Address Register Channel 1, least
0x2C
IAR1H
DMA I/O Address Register Channel 1, most
0x2D
Reserved
0x2E
BCR1L
DMA Byte Count Register Channel 1, least
0x2F
BCR1H
DMA Byte Count Register Channel 1, most
0x30
DSTAT
DMA Status Register
0x31
DMODE
DMA Mode Register
0x32
DCNTL
DMA/WAIT Control Register
0x33
IL
Interrupt Vector Low Register
0x34
ITC
Interrupt/Trap Control Register
0x35
Reserved
0x36
RCR
Refresh Control Register
0x37
Reserved
0x38
CBR
MMU Common Base Register
0x39
BBR
MMU Bank Base Register
0x3A
CBAR
MMU Common/ Bank Area Register
0x3B–0x3D
Reserved
0x3E
OMCR
Operation Mode Control Register
0x3F
ICR
I/O Control Register
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