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參數(shù)資料
| 型號： | 18V512JC |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable Configuration PROMs |
| 中文描述： | 在系統(tǒng)可編程配置PROM的 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 230K |
| 代理商： | 18V512JC |
XC18V00 Series In-System Programmable Configuration PROMs
2
1-800-255-7778Product SpecificationR
Pinout and Pin Description
Table 1
provides a list of the pin names and descriptions for the 44-pin VQFP and PLCC and the 20-pin SOIC and PLCC
packages.
Table 1:
Pin Names and Descriptions
Pin
Name
Boundary
Scan
Order
Function
Pin Description
44-pin
VQFP
44-pin
PLCC
20-pin
SOIC &
PLCC
D0
4
DATA OUT
D0 is the DATA output pin to provide data
for configuring an FPGA in serial mode.
40
2
1
3
OUTPUT
ENABLE
D1
6
DATA OUT
D0-D7 are the output pins to provide
parallel data for configuring a Xilinx
FPGA in Slave-Parallel/SelectMap mode.
D1-D7 remain in HIGHZ state when the
PROM operates in serial mode.
D1-D7 can be left unconnected when the
PROM is used in serial mode.
29
35
16
5
OUTPUT
ENABLE
D2
2
DATA OUT
42
4
2
1
OUTPUT
ENABLE
D3
8
DATA OUT
27
33
15
7
OUTPUT
ENABLE
D4
24
DATA OUT
9
15
7
(1)
23
OUTPUT
ENABLE
D5
10
DATA OUT
25
31
14
9
OUTPUT
ENABLE
D6
17
DATA OUT
14
20
9
16
OUTPUT
ENABLE
D7
14
DATA OUT
19
25
12
13
OUTPUT
ENABLE
CLK
0
DATA IN
Each rising edge on the CLK input
increments the internal address counter if
both CE is Low and OE/RESET is High.
43
5
3
OE/
RESET
20
DATA IN
When Low, this input holds the address
counter reset and the DATA output is in a
high-impedance state. This is a
bidirectional open-drain pin that is held
Low while the PROM is reset. Polarity is
NOT programmable.
13
19
8
19
DATA OUT
18
OUTPUT
ENABLE
CE
15
DATA IN
When CE is High, the device is put into
low-power standby mode, the address
counter is reset, and the DATA pins are
put in a high-impedance state.
15
21
10
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