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| 型號(hào)： | 16F630 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 14-Pin FLASH-Based 8-Bit CMOS Microcontrollers |
| 中文描述： | 14引腳基于閃存的8位CMOS微控制器 |
| 文件頁(yè)數(shù)： | 35/132頁(yè) |
| 文件大?。?/td> | 2651K |
| 代理商： | 16F630 |
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2003 Microchip Technology Inc.
DS40039C-page 33
PIC16F630/676
5.1
Timer1 Modes of Operation
Timer1 can operate in one of three modes:
16-bit timer with prescaler
16-bit synchronous counter
16-bit asynchronous counter
In Timer mode, Timer1 is incremented on every instruc-
tion cycle. In Counter mode, Timer1 is incremented on
the rising edge of the external clock input T1CKI. In
addition, the Counter mode clock can be synchronized
to
the
microcontroller
asynchronously.
system
clock
or
run
In Counter and Timer modules, the counter/timer clock
can be gated by the T1G input.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC w/o CLKOUT),
Timer1 can use the LP oscillator as a clock source.
5.2
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit (PIR1<0>) is set. To
enable the interrupt on rollover, you must set these bits:
Timer1 interrupt Enable bit (PIE1<0>)
PEIE bit (INTCON<6>)
GIE bit (INTCON<7>).
The interrupt is cleared by clearing the TMR1IF in the
Interrupt Service Routine.
5.3
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4, or 8
divisions of the clock input. The T1CKPS bits
(T1CON<5:4>) control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
FIGURE 5-2:
TIMER1 INCREMENTING EDGE
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge.
Note:
The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note
1:
2:
Arrows indicate counter increments.
In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the
clock.
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