參數(shù)資料
型號(hào)： 16F630
廠商： Microchip Technology Inc.
英文描述： 14-Pin FLASH-Based 8-Bit CMOS Microcontrollers
中文描述： 14引腳基于閃存的8位CMOS微控制器
文件頁數(shù)： 26/132頁
文件大?。?/td> 2651K
代理商： 16F630
PIC16F630/676
DS40039C-page 24
2003 Microchip Technology Inc.
3.2.3.5
RA4/AN3/T1G/OSC2/CLKOUT
Figure 3-4 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following:
a general purpose I/O
an analog input for the A/D (PIC16F676 only)
a TMR1 gate input
a crystal/resonator connection
a clock output
FIGURE 3-4:
BLOCK DIAGRAM OF RA4
3.2.3.6
RA5/T1CKI/OSC1/CLKIN
Figure 3-5 shows the diagram for this pin. The RA5 pin
is configurable to function as one of the following:
a general purpose I/O
a TMR1 clock input
a crystal/resonator connection
a clock input
FIGURE 3-5:
BLOCK DIAGRAM OF RA5
I/O pin
V
DD
V
SS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
V
DD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
Interrupt-on-Change
F
OSC
/4
To A/D Converter
Oscillator
Circuit
OSC1
CLKOUT
Enable
0
1
CLKOUT
Enable
Analog
Input Mode
RAPU
RD PORTA
To TMR1 T1G
INTOSC/
RC/EC
(2)
CLK
(1)
Modes
CLKOUT
Enable
Note 1:
CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2:
With CLKOUT option.
I/O pin
V
DD
V
SS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
V
DD
D
EN
Q
D
EN
Q
Weak
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
Interrupt-on-Change
To TMR1 or CLKGEN
INTOSC
Mode
RD PORTA
INTOSC
Mode
RAPU
Oscillator
Circuit
OSC2
(1)
Note
1:
Timer1 LP Oscillator enabled
2:
When using Timer1 with LP oscillator, the Schmitt
Trigger is by-passed.
TMR1LPEN
(1)
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