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參數(shù)資料
| 型號： | 0W344-004-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 39/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | DSP BELASIGNA 200 AUDIO 52-NQFN |
| 產(chǎn)品變化通告： | BelaSigna 200 QFN Obsolescence 09/Dec/2009 |
| 標準包裝： | 500 |
| 系列： | BelaSigna® 200 |
| 類型： | 音頻處理器 |
| 應用： | 便攜式設備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-TFQFN 裸露焊盤 |
| 供應商設備封裝： | 52-NQFP（8x8） |
| 包裝： | 帶卷 (TR) |
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BelaSigna 200
digital pads of BelaSigna 200 itself. Analog ground returns associated with the audio output stage should connect back to the star point
on separate individual traces.
For more information on the recommended ground design strategy, see Table 1.
In some designs, space constraints may make separate ground planes impractical. In this case a star configuration strategy should be
used. Each analog ground return should connect to the star point with separate traces.
3.2 Internal Power Supplies
Power management circuitry in BelaSigna 200 generates separate digital (VDDC) and analog (VREG, VDBL) regulated supplies. Each
supply requires an external decoupling capacitor, even if the supply is not used externally. Decoupling capacitors should be placed as
close as possible to the power pads. Further details are provided in Table 1. Non-critical signals are outlined in Table 2.
Table 1: Critical Signal
Pin Name
Description
Routing Guideline
VBAT
Power supply
Place 1μF (min) decoupling capacitor close to pin. Connect negative
terminal of capacitor to DGND plane.
VREG, VDBL
Internal regulator for analog
sections
Place separate 1μF decoupling capacitors close to each pin. Connect
negative capacitor terminal to AGND. Keep away from digital traces and
output traces. VREG may be used to generate microphone bias. VDBL
shall not be used to supply external circuitry.
AGND
Analog ground return
Connect to AGND plane.
VDDC
Internal regulator for digital
sections
Place 10μF decoupling capacitor close to pin. Connect negative terminal
of capacitor to DGND. Should be connected to VDDO pins and to
EEPROM power.
GNDO, GNDC
Digital ground return (pads and
core)
Connect to digital ground.
AI0, AI1 / LOUT, AI2, AI3
Microphone inputs
Keep as short as possible. Keep away from all digital traces and audio
outputs. Avoid routing in parallel with other traces. Connect unused inputs
to AGND.
AIR
Input stage reference voltage
Connect to AGND. If no analog ground plane, should share trace with
microphone grounds to star point.
AO0, AO1
Analog audio output
Keep away from microphone inputs.
RCVR0+, RCVR0-, RCVR1+,
RCVR1-
Direct digital audio output
Keep away from analog traces, particularly microphone inputs.
Corresponding traces should be of approximately the same length.
AOR
Output stage reference voltage
Connect to star point. Share trace with power amplifier (if present).
RCVRGND
Output stage ground return
Connect to star point.
EXT_CLK
External clock input / internal
clock output
Minimize trace length. Keep away from analog signals. If possible,
surround with digital ground.
AI_RC
Infrared receiver input
If used, minimize trace length to photodiode.
Rev. 16 | Page 5 of 43 | www.onsemi.com
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