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參數(shù)資料
| 型號(hào)： | μPD78F9801 |
| 廠商： | NEC Corp. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8 Bit Single Chip Microcontrollers |
| 中文描述： | 8位單片機(jī)微控制器 |
| 文件頁數(shù)： | 107/215頁 |
| 文件大?。?/td> | 764K |
| 代理商： | ΜPD78F9801 |
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CHAPTER 8 USB FUNCTION
107
(1)
Receive bank switching ID detection buffer (internal buffer)
This is an internal 2-bit buffer placed before a receive buffer. It detects the lower 2 bits below the packet ID
during packet receive and determines the store bank of a packet.
The following controls are performed depending on the stored 2-bit data. For details, see
Section 8.5.3
.
<1>
If the first 2 bits of the stored bits (low-order 2 bits in ID area) are 01B, TOSTAT (Bit 0 of the packet
receive status register (RXSTAT)) indicating the token packet receive is set and a signal specifying
packet store to the token packet receive is output to the send/receive pointer.
<2>
If the first 2 bits of the stored bits are 11B, DASTAT (Bit 1 of RXSTAT) indicating data packet receive is
set and a signal specifying packet store to the receive data address is sent to the send/receive pointer.
<3>
If the first 2 bits of the stored bits are 10B, HSSTAT (Bit 2 of RXSTAT) indicating the handshake
packet receive is set and a signal specifying packet store to the receive data address is output to the
send/receive pointer.
(2)
Send/receive pointer (USBPOB and USBPOW)
The USBPOB is a pointer of the bit side in the send/receive buffer and the USBPOW is a pointer of the
word side. The USBPOB and USBPOW output a control signal to the CRC circuit, etc.
They are reset and started by the packet ID detection signal from the receive bank switching ID detection
buffer.
USBPOB is incremented by the USB clock. USBPOW is incremented by USBPOB overflow.
USBPOW is read with an 8-bit memory manipulation instruction. As USBPOB is an internal pointer, control
with software is not possible.
RESET input sets these pointers to 00H.
The value of USBPOW is changed as follows depending on the receive/send byte length match signal or
send reservation. Moreover, control signals are also output. For details, see
Section 8.5.2
.
If the token packet receive signal is detected by the receive bank switching ID detection buffer, the
pointers are set to 00H.
If the data/handshake packet receive signal is detected by the receive bank switching ID detection buffer,
the pointers are set to 10H.
If USBPOW is set to 01H, a signal specifying CRC5 (CRC5 bit mode) execution start is output.
If USBPOW is set to 11H, 21H, or 31H, a signal specifying CRC16 (CRC16 bit mode) execution start is
output.
If USBPOB is set to 02H after USBPOW is set to 02H, a signal specifying CRC5 execution start is output
and the USBPOW is set to 70H.
If the value of USBPOW matches that of the data/handshake packet receive byte number counter
(DRXCON), a signal specifying CRC16 comparison start is output when USBPOB overflows, and
USBPOW is set to 70H.
If a signal specifying send start is received from the send control circuit, USBPOW is set to 7FH. After
that, USBPOW is set to 20H, 30H, 40H, 50H, or 60H depending on the error between the present send
reservation and previous receive data, when USBPOB overflows.
If the value of USBPOW matches that of data packet send byte number counter 0 (DTXCO0) or data
packet send byte number counter 1 (DTXCO1), USBPOW is set to 70H when USBPOB overflows (CRC
redundant bit is appended).
USBPOW is set to 71H, then a signal specifying EOP send is output when USBPOB overflows.
When USBPOW is set to 40H, 50H, or 60H, a signal specifying EOP send is output if USBPOB overflows.
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