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參數(shù)資料
| 型號(hào)： | μPD784225Y |
| 廠商： | NEC Corp. |
| 英文描述： | 16 Bit Single Chip Microcontrollers(16 位單片微控制器) |
| 中文描述： | 16位單片機(jī)微控制器（16位單片微控制器） |
| 文件頁(yè)數(shù)： | 29/68頁(yè) |
| 文件大?。?/td> | 278K |
| 代理商： | ΜPD784225Y |
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29
μ
PD784224Y, 784225Y
Table 7-1. Port Functions
Port Name
Pin Name
Function
Specification of Pull-up Resistor
Connection by Software
Port 0
P00-P05
Can be set in input or output mode bit-wise
Can be specified bit-wise
Port 1
P10-P17
Input port
—
Port 2
P20-P27
Can be set in input or output mode bit-wise
Can be specified bit-wise
Port 3
P30-P37
Can be set in input or output mode bit-wise
Can be specified bit-wise
Port 4
P40-P47
Can be set in input or output mode bit-wise
Can directly drive LEDs
Can be specified in 1-port units
Port 5
P50-P57
Can be set in input or output mode bit-wise
Can directly drive LEDs
Can be specified in 1-port units
Port 6
P60-P67
Can be set in input or output mode bit-wise
Can be specified in 1-port units
Port 7
P70-P72
Can be set in input or output mode bit-wise
Can be specified bit-wise
Port 12
P120-P127
Can be set in input or output mode bit-wise
Can be specified bit-wise
Port 13
P130, P131
Can be set in input or output mode bit-wise
—
7.2 Clock Generation Circuit
An on-chip clock generation circuit necessary for operation is provided. This clock generation circuit has a divider
circuit. If high-speed operation is not necessary, the internal operating frequency can be lowered by the divider
circuit to reduce the current consumption.
Figure 7-2. Block Diagram of Clock Generation Circuit
XT2
XT1
X1
X2
STOP
Main system
clock
oscillation
circuit
Subsystem
clock
oscillation
circuit
f
XT
Watch timer,
clock output function
Clock to
peripheral hardware
CPU
clock
(f
CPU
)
Divider
circuit
Prescaler
Prescaler
Standby
control
circuit
Wait
control
circuit
f
X
f
X
2
f
XX
2
f
XX
2
2
f
XX
2
3
f
XX
S
S
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