
477
CHAPTER 18 STANDBY FUNCTION
18.5 IDLE Mode
18.5.1 IDLE mode setting and operating states
The IDLE mode is selected by setting (1) both the STP bit and the HLT bit of the standby control (STBC) register.
The only writes that can be performed on the STBC are 8-bit data writes by means of a dedicated instruction. IDLE mode
setting is therefore performed by means of the “MOV STBC, #byte” instruction.
Caution If a condition that releases the HALT mode comes into effect when the IDLE mode is being set (refer
to 18.3.2 HALT mode release), the IDLE mode is not entered, and the next instruction is executed, or
a branch to a vectored interrupt service program is performed. Before this branch execution, the
instructions after the IDLE mode setting may be executed for 6 clocks. After restoring from the
interrupt service, to execute an instruction after setting the IDLE mode, insert 3 NOP instructions
before the instruction. To be sure to set the IDLE mode, take the necessary precautions such as
clearing the interrupt request before setting the IDLE mode.
Table 18-5. Operating States in IDLE Mode
Clock oscillator
Oscillation continues
Internal system clock
Stopped
CPU
Operation stopped
I/O lines
Retain state prior to IDLE mode setting
Peripheral functions
All operation stopped
Note
Internal RAM
Retained
Bus lines
AD0 to AD15
High-impedance
A16 to A19
High-impedance
RD, LWR, HWR output
High-impedance
ASTB output
High-impedance
Note
A/D converter operation is stopped, but if the AM0 bit or AM1 bit of the A/D converter mode register (ADM) is
set, the current consumption does not decrease.
Caution Stop the A/D converter (by clearing (0) the AM0 and AM1 bits of the A/D converter mode register (ADM))
before setting the IDLE mode.