
CHAPTER 9 TIMER 1
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(1) Timer register 1 (TM1)
TM1 is a timer register that counts up the count clock specified by the prescaler mode register (PRM).
Counting of this timer register is enabled or disabled by the timer mode control register (TMC).
The timer register can be only read by using a 16-bit manipulation instruction. When RESET is input, TM1 is cleared
to 0000H and stops counting.
(2) Compare registers (CM10, CM11)
CM1n (n = 0, 1) is a 16-bit register that holds the value determining the cycle of the interval timer operation.
When the contents of CM1n matches with the contents of TM1, an interrupt request (INTCM1n: n = 0, 1) and a timer
output control signal are generated. The count value of TM1 can be cleared when its value matches with the contents
of CM10.
These compare registers can be read or written by using 16-bit manipulation instructions. When RESET is input,
their contents are undefined.
(3) Output control circuit
When the contents of CM1n (n = 0, 1) and the contents of TM1 match, the timer output can be inverted. A square
wave can be output from a timer output pin (TO10, TO11) if so specified by the timer output control register 1 (TOC1).
The TO10 pin can also output a set and reset signals if so specified by the timer unit mode register 0 (TUM0).
The timer output can be enabled or disabled by TOC1. When the timer output is disabled, a fixed level is output
to the TO1n (n = 0, 1) pin (the output level is fixed by TOC1).
(4) Prescaler
The prescaler generates a count clock by dividing the internal system clock. The clock generated by the prescaler
is selected by the selector, and TM1 performs the count operation by using this clock as a count clock.
(5) Selector
The selector selects one of the five signals generated by dividing the internal system clock as the count clock of
TM1.