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CHAPTER 18 INTERRUPT FUNCTIONS
317
Figure 18-11. Interrupt Request Acceptance Timing (Example of MOV A,r)
If an interrupt request flag (
××
IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n
1,
the interrupt is accepted after the instruction under execution completes. Figure 18-11 shows an example of the
interrupt request acceptance timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is executed
for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acceptance processing is
performed after the MOV A,r instruction is completed.
Figure 18-12. Interrupt Request Acceptance Timing (When Interrupt Request Flag Generates at the Last
Clock During Instruction Execution)
If an interrupt request flag (
××
IF) is set at the last clock of the instruction, the interrupt acceptance processing
starts after the next instruction is executed. Figure 18-12 shows an example of the interrupt acceptance timing for
an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A,r
instruction after the NOP instruction is executed, and then the interrupt acceptance processing is performed.
Caution
Interrupt requests are reserved while the interrupt request flag register (IF0 to IF2) or the
interrupt mask flag register (MK0 to MK2) is being accessed.
18.4.3 Multiplexed interrupt processing
Multiplexed interrupt processing in which another interrupt is accepted while an interrupt is processed can be
processed by priority. When two or more interrupts are generated at once, interrupt processing is performed
according to the priority assigned to each interrupt request in advance (see
Table 18-1
).
Clock
CPU
Interrupt
MOV A,r
Saving PSW and PC, Jump
to Interrupt Processing
8 Clocks
Interrupt Processing Program
Saving PSW and PC, Jump
to Interrupt Processing
8 Clocks
Interrupt
Processing
Program
Clock
CPU
Interrupt
NOP
MOV A,r