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CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER
Figure 12-2. Format of LCD Display Mode Register
(
μ
PD780308, 780308Y subseries)
LCDM2 LCDM1LCDM0
Time division
Bias
0
0
0
4
1/3
0
0
1
3
1/3
0
1
0
2
1/2
0
1
1
3
1/2
1
0
0
Static
Others
Setting prohibited
Supply voltage of LCD controller/driver
Static display mode
1/3 bias mode
1/2 bias mode
0
Normal operation
2.0 to 5.5 V
2.5 to 5.5 V
2.7 to 5.5 V
1
Low-voltage operation 2.0 to 3.4 V
LCDM6 LCDM5 LCDM4
Selects LCD clock
Note
At f
XX
= 5.0 MHz
At f
XX
= 4.19 MHz
At f
XT
= 32.768 kHz
0
0
0
f
W
/2
9
(76 Hz)
f
W
/2
9
(64 Hz)
f
W
/2
9
(64 Hz)
0
0
1
f
W
/2
8
(153 Hz)
f
W
/2
8
(128 Hz)
f
W
/2
8
(128 Hz)
0
1
0
f
W
/2
7
(305 Hz)
f
W
/2
7
(256 Hz)
f
W
/2
7
(256 Hz)
0
1
1
f
W
/2
6
(610 Hz)
f
W
/2
6
(512 Hz)
f
W
/2
6
(512 Hz)
Others
Setting prohibited
LDON
Enables/disables LCD display
0
Display off (all segment outputs are unselect signal outputs)
1
Display on
Notes 1.
To lower the power consumption, clear LCDM3 to 0 when LCD display is not used. To manipulate
LCDM3, be sure to turn off the LCD display.
If TMC21 is cleared to 0 during LCD display, the supply of the LCD clock is stopped and the display
is disturbed.
2.
The LCD clock is supplied by the watch timer. To perform LCD display, set the bit 1 (TMC21) of watch
timer mode control register (TMC2) to 1.
If TMC21 is reset to 0 during LCD display, supply of the LCD clock is stopped and the display is disturbed.
Remarks 1.
f
W
: watch timer clock frequency (f
XX
/2
7
or f
XT
)
2.
f
XX
: main system clock frequency (f
X
or f
X
/2)
3.
f
X
: main system clock oscillation frequency
4.
f
XT
: subsystem clock oscillation frequency
7
6
5
4
3
2
Symbol
1
0
FFB0H
LCDM0
LCDM
LCDM1
LCDM3 LCDM2
LCDM4
LCDM5
LCDM6
LCDON
Address
At reset
R/W
00H
R/W
LCDM3
Note 1
Operation mode of
LCD controller/driver