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CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE
Figure 8-10. Format of Serial Bus Interface Control Register
(
μ
PD78054Y, 78064Y, 78078Y, 780058Y, 780308Y, 78058FY, 78075BY
subseries,
μ
PD78070AY) (1/2)
R/W
RELT
Used to output stop condition.
When RELT = 1, SO latch is set to 1. After SO latch has been set, this bit is automatically cleared to
0. It is also cleared to 0 when CSIE0 = 0.
R/W CMDT Used to output start condition.
When CMDT = 1, SO latch is cleared to 0. After SO latch has been cleared, this bit is automatically
cleared to 0. It is also cleared to 0 when CSIE0 = 0.
R
RELD
Stop condition detection
Clear condition (RELD = 0)
Set condition (RELD = 1)
On execution of transfer start instruction
Stop condition is detected
If values of SIO0 and SVA do not coincide when
address is received
When CSIE0 = 0
At RESET input
R
CMDD
Start condition detection
Clear condition (CMDD = 0)
Set condition (CMDD = 1)
On execution of transfer start instruction
When start condition is detected
When stop condition is detected
When CSIE0 = 0
At RESET input
R/W ACKT
Makes SDA0 (SDA1) low immediately after instruction that sets this bit to 1 (ACKT = 1) until next
SCL falls. Used to generate ACK signal by software when 8-clock wait is selected.
Cleared to 0 when transfer by serial interface is started and CSIE0 = 0
Note
Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
Remark
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
7
6
5
4
3
2
Symbol
1
0
FF61H
RELT
SBIC
CMDT
CMDD RELD
ACKT
ACKE
ACKD
BSYE
Address
At reset
R/W
00H
R/W
Note