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CHAPTER 23
μ
PD78P018F, 78P018FY
(3) Standby mode
The standby mode is set when CE = H.
In this mode, the data output goes into a high-impedance state regardless of the status of OE.
(4) Page data latch mode
The page data latch mode is set when CE = H, PGM = H, and OE = L at the beginning of the page write mode.
In this mode, 4-byte data of 1 page is latched to the internal address/data latch circuit.
(5) Page write mode
Page write is executed by applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H and OE
= H after latching 1-page, 4-byte address and data in the page data latch mode. After that, the program can
be verified when CE = L and OE = L.
If the program cannot be written by one program pulse, repeatedly execute write and verify X times (X
≤
10).
(6) Byte write mode
Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L and
OE = H. After that, the program can be verified when OE = L.
If the program cannot be written by one program pulse, repeatedly execute write and verify X times (X
≤
10).
(7) Program verify mode
The program verify mode is set when CE = L, PGM = H, and OE = L.
Use this mode to confirm that the program has written correctly.
(8) Program inhibit mode
The program inhibit mode is used to write one device of the plural
μ
PD78P018F’s and 78P018FY’s whose
OE, V
PP
, and D0-D7 pins are connected in parallel.
To write a program, use the page write or byte write mode described above. At this time, the program is not
written to a device whose PGM pin is high.