
341
CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
μ
PD78018FY SUBSERIES)
(c) Interrupt timing specification register (SINT)
SINT is set by using a 1-bit or 8-bit memory manipulation instruction.
This register is set to 00H when the RESET signal is input.
(Cont’d)
Notes 1.
Bit 6 (CLD) is read-only bit.
2.
Set WAT1 and WAT0 to 1, 0 or 1, 1 in the I
2
C bus mode.
7
<6>
<5>
<4>
<3>
<2>
Symbol
1
0
FF63H
WAT0
SINT
WAT1
CLC
WREL
SVAM
SIC
CLD
0
Address
On reset
R/W
00H
R/W
Note 1
WAT1
Controls wait and interrupt
Note 2
0
Generates interrupt processing request at rising edge of 8th clock of SCK0 (clock output goes
to high-impedance state)
R/W
0
Setting prohibited
WAT0
0
1
1
Used in I
2
C bus mode (8-clock wait).
Generates interrupt processing request at rising edge of 8th clock of SCL. (After outputting 8
clocks, master makes SCL output low and waits. After inputting 8 clocks, slave makes SCL pin
low and requests wait.)
0
1
Used in I
2
C bus mode (9-clock wait).
Generates interrupt processing request at rising edge of 9th clock of SCL. (After outputting 9
clocks, master makes SCL output low and waits. After inputting 9 clocks, slave makes SCL pin
low and requests wait.)
1
WREL
Controls releasing wait
0
Wait released status
R/W
1
Released wait status.
This bit is automatically cleared to 0 after wait status has been released (used to release wait status set
by WAT0, WAT1).
CLC
Controls clock level
0
Used in I
2
C bus mode.
Makes output level of SCL pin low when serial transfer is not executed.
R/W
1
Used in I
2
C bus mode.
Puts output level of SCL pin in high-impedance state when serial transfer is not executed (the clock line is
high).
Master uses this setting to make SCL high to generate start/stop condition.