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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
μ
PD78018FY SUBSERIES)
(4) Interrupt timing specification register (SINT)
This register controls the interrupt, wait and clock level, sets address mask function, and indicates the status
of the level of the SCK0/SCL/P27 pin.
SINT is set by a 1-bit or 8-bit memory manipulation instruction.
This register is set to 00H when the RESET signal is input.
Figure 16-5. Format of Interrupt Timing Specification Register (1/2)
Notes 1.
Bit 6 (CLD) is read-only bit.
2.
Set CLC to 0 when the I
2
C bus mode is not used.
<6>
<5>
<4>
<3>
<2>
1
0
7
Symbol
SINT
0
CLD
SIC
SVAM CLC WREL WAT1 WAT0
FF63H 00H
R/W
Note 1
Address On reset R/W
WAT1
0
Controls wait and interrupt
Generates interrupt processing request at rising edge of 8th clock of SCK0 (clock output goes to
high-impedance state)
WREL
0
Controls clearing wait
Wait clear status
Clears wait status.
This bit is automatically cleared to 0 after wait status has been cleared (used to clear wait status set by
WAT0, WAT1)
CLC
0
1
Controls clock level
Note 2
Used in I
2
C bus mode.
Makes output level of SCL pin low when serial transfer is not executed.
Used in I
2
C bus mode.
Puts output level of SCL pin in high-impedance state when serial transfer is not executed (the clock line is
high).
Master uses this setting to make SCL high to generate start/stop condition.
R/W
R/W
R/W
1
WAT0
0
0
1
Setting prohibited
1
0
Used in I
2
C bus mode (8-clock wait).
Generates interrupt processing request at rising edge of 8th clock of SCL (master makes SCL output
low and waits after outputting 8 clocks. Slave makes SCL pin low and requests for wait after inputting
8 clocks).
1
1
Used in I
2
C bus mode (9-clock wait).
Generates interrupt processing request at rising edge of 9th clock of SCL (master makes SCL output
low and waits after outputting 9 clocks. Slave makes SCL pin low land requests for wait after inputting
9 clocks).