
216
CHAPTER 9 8-BIT TIMER/EVENT COUNTER
Caution Even when the two 8-bit timers are used in combination in a 16-bit timer/event counter mode,
when the count value of TM1 coincides with the value of CR10, an interrupt request (INTTM1)
is generated, and the F/F of the 8-bit timer/event counter output control circuit 1 is inverted.
When using the 8-bit timers as a 16-bit interval timer, set mask flag TMMK1, which disables
accepting INTTM1, to 1.
To read the count value of the 16-bit timer register (TMS), use a 16-bit memory manipulation
instruction.
Table 9-9. Interval Time when Two 8-Bit Timer/Event Counters (TM1 and TM2)
Are Used as One 16-Bit Timer/Event Counter
TCL13
TCL12
TCL11
TCL10
Minimum Interval Time
Maximum Interval Time
Resolution
0
0
0
0
TI1 input cycle
2
8
×
TI1 input cycle
TI1 input edge cycle
0
0
0
1
TI1 input cycle
2
8
×
TI1 input cycle
TI1 input edge cycle
0
1
1
0
2
2
×
1/f
X
(400 ns)
2
18
×
1/f
X
(26.2 ms)
2
2
×
1/f
X
(400 ns)
0
1
1
1
2
3
×
1/f
X
(800 ns)
2
19
×
1/f
X
(52.4 ms)
2
3
×
1/f
X
(800 ns)
1
0
0
0
2
4
×
1/f
X
(1.6
μ
s)
2
20
×
1/f
X
(104.9
ms)
2
4
×
1/f
X
(1.6
μ
s)
1
0
0
1
2
5
×
1/f
X
(3.2
μ
s)
2
21
×
1/f
X
(209.7 ms)
2
5
×
1/f
X
(3.2
μ
s)
1
0
1
0
2
6
×
1/f
X
(6.4
μ
s)
2
22
×
1/f
X
(419.4 ms)
2
6
×
1/f
X
(6.4
μ
s)
1
0
1
1
2
7
×
1/f
X
(12.8
μ
s)
2
23
×
1/f
X
(838.9 ms)
2
7
×
1/f
X
(12.8
μ
s)
1
1
0
0
2
8
×
1/f
X
(25.6
μ
s)
2
24
×
1/f
X
(1.7 s)
2
8
×
1/f
X
(25.6
μ
s)
1
1
0
1
2
9
×
1/f
X
(51.2
μ
s)
2
25
×
1/f
X
(3.4 s)
2
9
×
1/f
X
(51.2
μ
s)
1
1
1
0
2
10
×
1/f
X
(102.4
μ
s)
2
26
×
1/f
X
(6.7 s)
2
10
×
1/f
X
(102.4
μ
s)
1
1
1
1
2
12
×
1/f
X
(409.6
μ
s)
2
28
×
1/f
X
(26.8 s)
2
12
×
1/f
X
(409.6
μ
s)
Others
Setting prohibited
Remarks
1.
f
X
2.
TCL10-TCL13: Bits 0 through 3 of timer clock select register 1 (TCL1)
3.
( )
: At f
X
= 10.0 MHz operation
: Main system clock oscillation frequency