
488
CHAPTER 24 INSTRUCTION SET
Clock
Flag
Note 1
Note 2
Z AC CY
BTCLR
saddr.bit, $addr16
4
20
24
PC
←
PC + 4 + jdisp8 if(saddr.bit) = 1
then reset(saddr.bit)
sfr.bit, $addr16
4
–
24
PC
←
PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr16
3
16
–
PC
←
PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr16
4
–
24
PC
←
PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
×
×
×
[HL].bit, $addr16
3
20
24 + 2n + 2m
PC
←
PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
DBNZ
B, $addr16
2
12
–
B
←
B – 1, then
PC
←
PC + 2 + jdisp8 if B
≠
0
C, $addr16
2
12
–
C
←
C –1, then
PC
←
PC + 2 + jdisp8 if C
≠
0
saddr, $addr16
3
16
20
(saddr)
←
(saddr) – 1, then
PC
←
PC + 3 + jdisp8 if(saddr)
≠
0
SEL
RBn
2
8
–
RBS1, 0
←
n
NOP
1
4
–
No operation
EI
2
–
12
IE
←
1(Enable interrupt)
DI
2
–
12
IE
←
0(Disable interrupt)
HALT
2
12
–
Set HALT mode
STOP
2
12
–
Set STOP mode
Notes 1.
When the internal high-speed RAM area is accessed or when an instruction that does not access data
is executed
2.
When an area other than the internal high-speed RAM area is accessed
Remarks 1.
One clock of an instruction is equal to one CPU clock (f
CPU
) selected by processor clock control
register (PCC).
2.
The number of clocks shown is when the program is stored in the internal ROM area.
3.
n indicates the number of wait states when the external memory extension area is read.
4.
m indicates the number of wait states when the external memory extension area is written.
24.3 Instruction List by Addressing
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Mnemonic
Operand
Byte
Operation
Conditional
branch
Instruction
Group
CPU
control