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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
μ
PD78018FY SUBSERIES)
(3) Serial bus interface control register (SBIC)
This register sets the operation of the serial bus interface and indicates the status.
SBIC is set by a 1-bit or 8-bit memory manipulation instruction.
This register is set to 00H when the RESET signal is input.
Figure 16-4. Format of Serial Bus Interface Control Register (1/2)
Note
Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
Remark
CSIE0: Bit 7 of the serial operation mode register 0 (CSIM0)
<6>
<5>
<4>
<3>
<2>
<1>
<0>
<7>
Symbol
SBIC
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
RELT
Used to output stop condition in I C bus mode.
SO0 latch is set to 1 when RELT = 1 . After setting SO0 latch, RELT is automatically cleared to 0.
This bit is also cleared to 0 when CSIE0 = 0.
R/W
FF61H 00H R/W
Note
Address On reset R/W
CMDT
Used to output start condition in I C bus mode.
SO0 latch is cleared to 0 when CMDT = 1. After clearing SO0 latch, CMDT is automatically cleared to 0.
This bit is also cleared to 0 when CSIE0 = 0.
R/W
R
RELD
Stop condition detection
Setting condition (RELD = 1)
Clearing conditions (RELD = 0)
When stop condition is detected in I C mode
When transfer start instruction is executed
When values of SIO0 and SVA do not coincide
when address is received
When CSIE0 = 0
When RESET is input
R
CMDD
Start condition detection
Clearing conditions (CMDD = 0)
When transfer start instruction is executed
When stop condition is detected in I C mode
When CSIE0 = 0
When RESET is input
Setting condition (CMDD = 1)
When start condition is detected in I C bus mode
2
2
2
2
2