
485
CHAPTER 24 INSTRUCTION SET
Clock
Flag
Note 1
Note 2
Z AC CY
ADJBA
2
8
–
Decimal Adjust Accumulator after
Addition
×
×
×
ADJBS
2
8
–
Decimal Adjust Accumulator after
Subtract
×
×
×
MOV1
CY, saddr.bit
3
12
14
CY
←
(saddr.bit)
×
CY, sfr.bit
3
–
14
CY
←
sfr.bit
×
CY, A.bit
2
8
–
CY
←
A.bit
×
CY, PSW.bit
3
–
14
CY
←
PSW.bit
×
CY, [HL].bit
2
12
14 + 2n CY
←
(HL).bit
×
saddr.bit, CY
3
12
16
(saddr.bit)
←
CY
sfr.bit, CY
3
–
16
sfr.bit
←
CY
A.bit, CY
2
8
–
A.bit
←
CY
PSW.bit, CY
3
–
16
PSW.bit
←
CY
×
×
[HL].bit, CY
2
12
16 + 2n + 2m
(HL).bit
←
CY
AND1
CY, saddr.bit
3
12
14
CY
←
CY
(saddr.bit)
×
CY, sfr.bit
3
–
14
CY
←
CY
sfr.bit
×
CY, A.bit
2
8
–
CY
←
CY
A.bit
×
CY, PSW.bit
3
–
14
CY
←
CY
PSW.bit
×
CY, [HL].bit
2
12
14 + 2n CY
←
CY
(HL).bit
×
OR1
CY, saddr.bit
3
12
14
CY
←
CY
(saddr.bit)
×
CY, sfr.bit
3
–
14
CY
←
CY
sfr.bit
×
CY, A.bit
2
8
–
CY
←
CY
A.bit
×
CY, PSW.bit
3
–
14
CY
←
CY
PSW.bit
×
CY, [HL].bit
2
12
14 + 2n CY
←
CY
(HL).bit
×
XOR1
CY, saddr.bit
3
12
14
CY
←
CY
(saddr.bit)
×
CY, sfr.bit
3
–
14
CY
←
CY
sfr.bit
×
CY, A.bit
2
8
–
CY
←
CY
A.bit
×
CY, PSW. bit
3
–
14
CY
←
CY
PSW.bit
×
CY, [HL].bit
2
12
14 + 2n CY
←
CY
(HL).bit
×
Notes 1.
When the internal high-speed RAM area is accessed or when an instruction that does not access data
is executed
2.
When an area other than the internal high-speed RAM area is accessed
Remarks 1.
One clock of an instruction is equal to one CPU clock (f
CPU
) selected by processor clock control
register (PCC).
2.
The number of clocks shown is when the program is stored in the internal ROM area.
3.
n indicates the number of wait states when the external memory extension area is read.
4.
m indicates the number of wait states when the external memory extension area is written.
Mnemonic
Operand
Byte
Operation
BCD
adjustment
Instruction
Group
Bit
manipulation