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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
μ
PD78018FY SUBSERIES)
(3) Signals
Figure 16-11 shows the operations of RELT and CMDT.
Figure 16-11. Operations of RELT and CMDT
(4) Transfer start
Serial transfer is started by setting the transfer data to the serial I/O shift register 0 (SIO0) when the following
two conditions are satisfied:
Operation control bit of serial interface channel 0 (CSIE0) = 1
When internal serial clock is stopped or SCK0 is high after 8-bit serial transfer
Cautions 1. Even if CSIE0 is set to “1” after data has been written to SIO0, transfer is not started.
2. Write FFH to SIO0 in advance because the N-ch open-drain output must be made high-
impedance state during data reception.
Serial transfer is automatically stopped at the end of 8-bit transfer, and an interrupt request flag (CSIIF0) is
set.
(5) Error detection
In the 2-wire serial I/O mode, the status of the serial bus SB0 (SB1) under transmission is also loaded to serial
I/O shift register 0 (SIO0) of the device that is transmitting data; therefore, a transfer error can be detected
by the following method:
(a) By comparing data of SIO0 before start of and after completion of transmission
In this case, it is judged that an transmission error has occurred if two data are different.
(b) By using slave address register (SVA)
The transmitted data is set to SIO0 and SVA and transmission is executed. After completion of
transmission, the COI bit (match signal from address comparator) of the serial operation mode register
0 (CSIM0) is tested. If this bit is “1”, it is judged that transmission has been completed normally. If it is
“0”, it is judged that a transmittion error has occurred.
RELT
CMDT
SO0 latch