484
CHAPTER 24 INSTRUCTION SET
Clock
Flag
Note 1
Note 2
Z AC CY
CMP
A, #byte
2
8
–
A – byte
×
×
×
saddr, #byte
3
12
16
(saddr) – byte
×
×
×
A, r
Note 3
2
8
–
A – r
×
×
×
r, A
2
8
–
r – A
×
×
×
A, saddr
2
8
10
A – (saddr)
×
×
×
A, !addr16
3
16
18 + 2n A – (addr16)
×
×
×
A, [HL]
1
8
10 + 2n A – (HL)
×
×
×
A, [HL + byte]
2
16
18 + 2n A – (HL + byte)
×
×
×
A, [HL + B]
2
16
18 + 2n A – (HL + B)
×
×
×
A, [HL + C]
2
16
18 + 2n A – (HL + C)
×
×
×
ADDW
AX, #word
3
12
–
AX, CY
←
AX + word
×
×
×
SUBW
AX, #word
3
12
–
AX, CY
←
AX – word
×
×
×
CMPW
AX, #word
3
12
–
AX – word
×
×
×
MULU
X
2
32
–
AX
←
A
×
X
DIVUW
C
2
50
–
AX (quotient), C (remainder)
←
AX
÷
C
INC
r
1
4
–
r
←
r + 1
×
×
saddr
2
8
12
(saddr)
←
(saddr) + 1
×
×
DEC
r
1
4
–
r
←
r – 1
×
×
saddr
2
8
12
(saddr)
←
(saddr) – 1
×
×
INCW
rp
1
8
–
rp
←
rp + 1
DECW
rp
1
8
–
rp
←
rp – 1
ROR
A, 1
1
4
–
(CY, A
7
←
A
0
, A
m – 1
←
A
m
)
×
1 time
×
ROL
A, 1
1
4
–
(CY, A
0
←
A
7
, A
m + 1
←
A
m
)
×
1 time
×
RORC
A, 1
1
4
–
(CY
←
A
0
, A
7
←
CY, A
m – 1
←
A
m
)
×
1 time
×
ROLC
A, 1
1
4
–
(CY
←
A
7
, A
0
←
CY, A
m + 1
←
A
m
)
×
1 time
×
ROR4
[HL]
2
20
24 + 2n + 2m
A
3 – 0
←
(HL)
3 – 0
, (HL)
7 – 4
←
A
3 – 0
,
(HL)
3 – 0
←
(HL)
7 – 4
ROL4
[HL]
2
20
24 + 2n + 2m
A
3 – 0
←
(HL)
7 – 4
, (HL)
3 – 0
←
A
3 – 0
,
(HL)
7 – 4
←
(HL)
3 – 0
Notes 1.
When the internal high-speed RAM area is accessed or when an instruction that does not access data
is executed
2.
When an area other than the internal high-speed RAM area is accessed
3.
Except r = A
Remarks 1.
One clock of an instruction is equal to one CPU clock (f
CPU
) selected by processor clock control
register (PCC).
2.
The number of clocks shown is when the program is stored in the internal ROM area.
3.
n indicates the number of wait states when the external memory extension area is read.
4.
m indicates the number of wait states when the external memory extension area is written.
Mnemonic
Operand
Byte
Operation
8-bit
operation
Instruction
Group
16-bit
operation
Multiply/
divide
Increment/
decrement
Rotate