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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
μ
PD78018FY SUBSERIES)
(4) Completion processing of reception by slave
Make sure that bit 3 (CMDD) of the serial bus interface control register (SBIC) and bit 6 (COI) of the serial
operation mode register 0 (CSIM0) (when CMDD = 1) are checked in the reception completion processing
of the slave (interrupt processing). This is to prevent the slave from being unable to identify whether the start
condition or data comes first and therefore to prevent the wake-up function from being unusable when a non-
specific amount of data is received from the master.
16.4.6 Restrictions in I
2
C bus mode
The following restrictions apply to the
μ
PD78018FY subseries.
Restrictions when used as slave device in I
2
C bus ode
Applicable models
μ
PD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY, 78P018FY,
and IE-78014-R-EM-A
Description
When the wake-up function is executed (by setting the WUP flag (bit 5 of the serial
operation mode register 0 (CSIM0)) in the serial transfer status
Note
, data between the
other slaves and master will be judged as an address. If this data happens to coincide
with the slave address of the
μ
PD78018FY subseries, the
μ
PD78018FY subseries will
initiate communication, destroying the communication data.
Note
The serial transfer status is the status in which the interrupt request flag (CSIIF0)
is set because of the end of serial transfer after the serial I/O shift register 0
(SIO0) has been written.
Preventive measure
This restriction can be avoided by modifying the program.
Before executing the wake-up function, execute the following program that releases
serial transfer status. To execute the wake-up function, do not execute an instruction
that writes SIO0. Even if such an instruction is not executed, data can be received when
the wake-up function is executed.
This program releases the serial transfer status. To release the serial transfer status,
the serial interface channel 0 must be set once in the operation stop status (by clearing
the CSIE0 flag (bit 7 of the serial operation mode register (CSIM0) to 0). However, if
the serial interface channel 0 is set in the operation stop status in the I
2
C bus mode,
the SCL pin output a high level and the SDA0 (SDA1) pin outputs a low level, affecting
communication of the I
2
C bus. Therefore, this program places the SCL and SDA0
(SDA1) pins in the high-impedance state to prevent the I
2
C bus from being affected.
In the example below, SDA0 (/P25) is used as a serial data input/output pin. When SDA1
(/P26) is used as the serial data input/output pin, take P2.5 and PM2.5 in the program
below as P2.6 and PM2.6, respectively
For the timing of each signal when this program is executed, refer to
Figure 16-21
.