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LIST OF FIGURES (1/3)
Figure No.
Title
Page
3-1
3-2
3-3
3-4
3-5
3-6
3-7
Selecting MBE = 0 Mode and MBE = 1 Mode.......................................................................
Configuration of Data Memory and Addressing Ranges of Respective Addressing Modes .
Updating Address of Static RAM...........................................................................................
Example of Using Register Banks.........................................................................................
Configuration of General-Purpose Registers (in 4-bit processing)........................................
Configuration of General-Purpose Registers (in 8-bit processing)........................................
m
PD750068 I/O Map .............................................................................................................
24
26
31
38
40
41
44
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
Format of Stack Bank Select Register ..................................................................................
Configuration of Program Counter ........................................................................................
Program Memory Map...........................................................................................................
Data Memory Map.................................................................................................................
Configuration of General-Purpose Register ..........................................................................
Configuration of Register Pair ...............................................................................................
Accumulator ..........................................................................................................................
Configuration of Stack Pointer and Stack Bank Select Register...........................................
Data Saved to Stack Memory (MkI Mode) ............................................................................
Data Restored from Stack Memory (MkI Mode)....................................................................
Data Saved to Stack Memory (MkII Mode) ...........................................................................
Data Restored from Stack Memory (MkII Mode)...................................................................
Configuration of Program Status Word .................................................................................
Configuration of Bank Select Register ..................................................................................
50
51
53
58
60
60
61
62
63
63
64
64
65
69
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
Data Memory Address of Digital Port....................................................................................
Configuration of Ports 0 and 1 ..............................................................................................
Configuration of Ports 3 and 6 ..............................................................................................
Configuration of Port .............................................................................................................
Configuration of Ports 4 and 5 ..............................................................................................
Configuration of Port 11 ........................................................................................................
Format of Each Port Mode Register......................................................................................
Format of Pull-up Resistor Specification Register.................................................................
I/O Timing of Digital I/O Port .................................................................................................
ON Timing of Internal Pull-up Resistor Connected via Software ..........................................
Block Diagram of Clock Generation Circuit ...........................................................................
Format of Processor Clock Control Register.........................................................................
Format of System Clock Control Register .............................................................................
External Circuit of Main System Clock Oscillation Circuit .....................................................
External Circuit of Subsystem Clock Oscillation Circuit Block Diagram of A/D Converter ....
Incorrect Example of Connecting Resonator ........................................................................
Subsystem Clock Oscillation Circuit......................................................................................
Format of Suboscillation Circuit Control Register (SOS) ......................................................
Selecting System Clock and CPU Clock...............................................................................
Block Diagram of Clock Output Circuit ..................................................................................
71
73
74
74
75
76
78
84
85
86
87
90
91
92
92
93
96
97
99
100