
– i –
TABLE OF CONTENTS
CHAPTER 1 GENERAL..................................................................................................................
1.1
Functional Outline...........................................................................................................
1.2
Ordering Information ......................................................................................................
1.3
Differences among
m
PD750068 Subseries Products..................................................
1.4
Block Diagram .................................................................................................................
1.5
Pin Connections (Top View) ..........................................................................................
1
2
3
3
4
5
CHAPTER 2 PIN FUNCTIONS .......................................................................................................
2.1
Pin Functions of
m
PD750068 .........................................................................................
2.2
Pin Functions...................................................................................................................
2.2.1
P00-P03 (PORT0), P10-P13 (PORT1), P110-P113 (PORT11) .......................................
2.2.2
P20-P23 (PORT2), P30-P33 (PORT3), P40-P43 (PORT4),
P50-P53 (PORT5), P60-P63 (PORT6) ..............................................................................
2.2.3
TI0, TI1 ... inputs shared with port 1 .................................................................................
2.2.4
PTO0, PTO1 ... outputs shared with port 2 ......................................................................
2.2.5
PCL ... output shared with port 2.......................................................................................
2.2.6
BUZ ... output shared with port 2 ......................................................................................
2.2.7
SCK, SO/SB0, and SI/SB1 ... 3-state I/Os shared with port 0 ........................................
2.2.8
INT4 ... input shared with port 0 ........................................................................................
2.2.9
INT0 and INT1 ... inputs shared with port 1......................................................................
2.2.10
INT2 ... input shared with port 1 ........................................................................................
2.2.11
KR0-KR3 ... inputs shared with port 6...............................................................................
2.2.12
AN0-AN3 ... inputs shared with port 11
AN4, AN7 ... inputs shared with port 6..............................................................................
2.2.13
AV
REF
...................................................................................................................................
2.2.14
AV
SS
.....................................................................................................................................
2.2.15
X1 and X2 ...........................................................................................................................
2.2.16
XT1 and XT2.......................................................................................................................
2.2.17
RESET.................................................................................................................................
2.2.18
MD0-MD3 (
m
PD75P0076 only) ..........................................................................................
2.2.19
D0-D7 (
m
PD75P0076 only) ................................................................................................
2.2.20
IC (
m
PD750064, 750066, and 750068 only) .....................................................................
2.2.21
V
PP
(
m
PD75P0076 only) .....................................................................................................
2.2.22
V
DD
.......................................................................................................................................
2.2.23
V
SS
.......................................................................................................................................
2.3
I/O Circuits of Respective Pins .....................................................................................
2.4
Processing of Unused Pins ...........................................................................................
7
7
11
11
12
13
13
13
13
13
13
14
14
15
15
15
15
15
16
16
16
16
17
17
17
17
18
21
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY .................................................
3.1
Bank Configuration of Data Memory and Addressing Mode ....................................
3.1.1
Bank configuration of data memory...................................................................................
3.1.2
Addressing mode of data memory.....................................................................................
3.2
Bank Configuration of General-Purpose Registers....................................................
3.3
Memory-Mapped I/O ........................................................................................................
23
23
23
25
37
42