
18
LIST OF FIGURES (4/4)
Figure
Title
Page
5-109
5-110
5-111
5-112
5-113
5-114
5-115
5-116
5-117
5-118
5-119
5-120
5-121
5-122
5-123
5-124
5-125
5-126
Common Signal Waveform (1/3 Bias method) .............................................................................. 280
Common and Segment Signal Electric Potentials and Phases ................................................... 281
LCD Drive Power Connection Examples (when split resistor is incorporated)........................... 283
LCD Drive Power Connection Examples (when split resistor is connected externally) ............. 284
Static Mode LCD Display Pattern and Electrode Connection ...................................................... 285
Static LCD Panel Connection Example.......................................................................................... 286
Static LCD Drive Waveform Example ............................................................................................ 287
Division by 2 Mode LCD Display Pattern and Electrode Connection.......................................... 288
Division by 2 LCD Panel Connection Example ............................................................................. 289
Division by 2 LCD Drive Waveform Example (1/2 Bias method)................................................. 290
Division by 3 Mode LCD Display Pattern and Electrode Connection.......................................... 291
Division by 3 LCD Panel Connection Example ............................................................................. 292
Division by 3 LCD Drive Waveform Example (1/2 Bias method)................................................. 293
Division by 3 LCD Drive Waveform Example (1/3 Bias method)................................................. 294
Division by 4 Mode LCD Display Pattern and Electrode Connection.......................................... 295
Division by 4 LCD Panel Connection Example ............................................................................. 296
Division by 4 LCD Drive Waveform Example (1/3 Bias method)................................................. 297
Bit Sequential Buffer Format........................................................................................................... 298
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
Interrupt Control Circuit Block Diagram ......................................................................................... 302
Interrupt Vector Table...................................................................................................................... 304
Interrupt Priority Selection Register ............................................................................................... 307
Configurations of INT0, INT1, and INT4 ........................................................................................ 309
Noise Eliminator Input/Output Timing ............................................................................................ 310
Edge Detection Mode Register Format.......................................................................................... 311
Interrupt Processing Sequence ...................................................................................................... 313
Multiple Interrupts by Higher-Order Priority Interrupts.................................................................. 314
Multiple Interrupts by Changing Interrupt Status Flag .................................................................. 315
INT2 and KR0 to KR3 Block Diagram ............................................................................................ 330
Format of INT2 Edge Detection Mode Register (IM2) .................................................................. 331
7-1
7-2
Standby Mode Release Operation ................................................................................................. 337
Wait Time when STOP Mode is Released .................................................................................... 339
8-1
8-2
Configuration of Reset Function ..................................................................................................... 347
Reset Operation by RESET Signal Generation............................................................................. 347
B-1
B-2
Package Drawing of EV-9200GC-64 (for reference only) ............................................................ 446
Recommended Footprint of EV-9200GC-64 (for reference only) ............................................... 447