
15
LIST OF FIGURES (1/4)
Figure
Title
Page
3-1
3-2
3-3
3-4
3-5
3-6
3-7
Selecting MBE = 0 Mode and MBE = 1 Mode ..............................................................................
Data Memory Configuration and Addressing Range for Each Addressing Mode.......................
Static RAM Address Update Method..............................................................................................
Example of Using Register Banks ..................................................................................................
General-Purpose Register Configuration (for 4-bit operation) .....................................................
General-Purpose Register Configuration (for 8-bit operation) .....................................................
μ
PD753108 I/O Map ........................................................................................................................
44
46
52
60
62
63
66
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
Stack Bank Selection Register Format ..........................................................................................
Program Counter Configuration ......................................................................................................
Program Memory Map .....................................................................................................................
Data Memory Map ...........................................................................................................................
Configuration of Display Data Memory ..........................................................................................
General-Purpose Register Configuration .......................................................................................
Register Pair Configuration .............................................................................................................
Accumulators ....................................................................................................................................
Stack Pointer and Stack Bank Selection Register Configuration ................................................
Data Saved in Stack Memory (Mk I mode)....................................................................................
Data Restored from Stack Memory (Mk I mode) ..........................................................................
Data Saved in Stack Memory (Mk II mode)...................................................................................
Data Restored from Stack Memory (Mk II mode) .........................................................................
Program Status Word Configuration ..............................................................................................
Bank Selection Register Configuration ..........................................................................................
72
73
75
81
83
84
84
85
86
87
87
88
88
89
93
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
Digital Ports Data Memory Addresses ...........................................................................................
Ports 0, 1 Configuration ..................................................................................................................
Ports 3, 6 Configuration ..................................................................................................................
Port 2 Configuration.........................................................................................................................
Port 5 Configuration.........................................................................................................................
Ports 8, 9 Configuration .................................................................................................................. 100
Port Mode Register Formats ........................................................................................................... 102
Pull-Up Resistor Specify Register Formats ................................................................................... 109
I/O Timing of Digital I/O Port .......................................................................................................... 110
ON Timing of On-Chip Pull-up Resistor Connected via Software ............................................... 111
Clock Generator Block Diagram ..................................................................................................... 112
Processor Clock Control Register Format ..................................................................................... 115
System Clock Control Register Format.......................................................................................... 116
Main System Clock Oscillator External Circuit .............................................................................. 117
Subsystem Clock Oscillator External Circuit ................................................................................. 117
Example of Connecting Resonator Incorrectly .............................................................................. 118
Subsystem Clock Oscillator ............................................................................................................ 121
Subsystem Clock Oscillator Control Register (SOS) Format ....................................................... 123
Switching between System Clock and CPU Clock........................................................................ 125
Clock Output Circuit Block Diagram ............................................................................................... 126
95
97
98
98
99