
15
LIST OF FIGURES (1/5)
Fig. No.
Title
Page
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
CPU Address Space...............................................................................................................................
Image on Address Space .......................................................................................................................
Memory Map...........................................................................................................................................
Internal ROM Area (with Mask ROM Internal Version)...........................................................................
External Memory Area (when expanded to 64 K, 256 K, or 1 Mbytes)...................................................
External Memory Area (when expanded to 4 Mbytes)............................................................................
Memory Expansion Mode Register (MM) Format...................................................................................
Memory Address Output Mode Register (MAM) Format ........................................................................
Recommended Memory Map (Flash Memory Internal Version).............................................................
59
60
62
63
67
68
70
71
74
4-1
Example of Inserting Wait States............................................................................................................
88
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
Non-Maskable Interrupt Processing .......................................................................................................
Accepting Non-Maskable Interrupt Request...........................................................................................
RETI Instruction Processing...................................................................................................................
Rising Edge Specification Register (EGP0) Format ...............................................................................
Falling Edge Specification Register (EGN0) Format ..............................................................................
Maskable Interrupt Processing...............................................................................................................
RETI Instruction Processing...................................................................................................................
Example of Interrupt Nesting Process....................................................................................................
Example of Processing Interrupt Requests Simultaneously Generated.................................................
Interrupt Control Register (xxICn) Format ..............................................................................................
Inservice Priority Register (ISPR) Format...............................................................................................
Watchdog Timer Mode Register (WDTM) Format..................................................................................
Software Exception Processing..............................................................................................................
RETI Instruction Processing...................................................................................................................
Exception Trap Processing.....................................................................................................................
RETI Instruction Processing...................................................................................................................
Pipeline Operation at Interrupt Request Acknowledge...........................................................................
105
106
107
109
109
111
112
114
116
117
119
120
122
123
125
126
130
6-1
6-2
6-3
Format of Processor Clock Control Register (PCC) ...............................................................................
Format of Power Saving Control Register (PSC)....................................................................................
Format of Oscillation Stabilization Time Select Register (OSTS)...........................................................
132
134
135
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
Block Diagram of TM0 and TM1.............................................................................................................
Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1).......................................................
Format of Capture/Compare Control Register 0, 1 (CRC0, CRC1)........................................................
Format of 16-Bit Timer Output Control Register 0, 1 (TOC0, TOC1)......................................................
Format of Prescaler Mode Register 0 (PRM0)........................................................................................
Format of Prescaler Mode Register 1 (PRM1)........................................................................................
Control Register Settings When Timer 0 Operates as Interval Timer.....................................................
Configuration of Interval Timer ...............................................................................................................
Timing of Interval Timer Operation.........................................................................................................
Control Register Settings in PPG Output Operation...............................................................................
146
151
153
155
156
157
158
159
159
160